使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Multiplexer為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Multiplexer為例(FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 assign HEX0=7'b111_1111;
 assign HEX1=7'b111_1111;
 assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
 
//module multiplexer_4_1(X, A0, A1, A2, A3, S1, S0);
//   parameter WIDTH=4;      // How many bits wide are the lines
//   output [WIDTH-1:0] X;   // The output line
//   input [WIDTH-1:0]  A3;  // Input line with id 2'b11
//   input [WIDTH-1:0]  A2;  // Input line with id 2'b10
//   input [WIDTH-1:0]  A1;  // Input line with id 2'b01
//   input [WIDTH-1:0]  A0;  // Input line with id 2'b00
//   input       S0;  // Least significant selection bit
//   input       S1;  // Most significant selection bit
multiplexer_4_1 U0(LEDR[3:0],SW[3:0],SW[7:4],SW[11:8],SW[15:12],SW[17],SW[16]);
endmodule  
module multiplexer_4_1(X, A0, A1, A2, A3, S1, S0);
   parameter WIDTH=4;      // How many bits wide are the lines
   output [WIDTH-1:0] X;   // The output line
   input [WIDTH-1:0]  A3;  // Input line with id 2'b11
   input [WIDTH-1:0]  A2;  // Input line with id 2'b10
   input [WIDTH-1:0]  A1;  // Input line with id 2'b01
   input [WIDTH-1:0]  A0;  // Input line with id 2'b00
   input       S0;  // Least significant selection bit
   input       S1;  // Most significant selection bit
   assign X = (S1 == 0 
       ? (S0 == 0 
  ? A0       // {S1,S0} = 2'b00
  : A1)      // {S1,S0} = 2'b01
       : (S0 == 0 
  ? A2       // {S1,S0} = 2'b10
  : A3));    // {S1,S0} = 2'b11   
endmodule // multiplexer_4_1