HBLbits_Verilog Basic_Edgedetect2
For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and anyedge[1] are shown separately
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] d;
always@(posedge clk) begin
d <= in;
anyedge <= d^in;
end
endmodule
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] d;
always@(posedge clk) begin
d <= in;
anyedge <= d^in;
end
endmodule
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