HBLbits_Verilog Basic_Gatesv100

HBLbits_Verilog Basic_Gatesv100 

You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:

out_both:

out_any:

out_different:

module top_module( 

    input [99:0] in,

    output [99:0] out_both,

    output [99:0] out_any,

    output [99:0] out_different );

     assign out_both = in[99:1] & in[98:0];

    assign out_any = in[99:1] | in[98:0];

    assign out_different = {in[0], in[99:1]} ^ in;

endmodule

// 另一種 方法

module top_module (

input [99:0] in,

output [98:0] out_both,

output [99:1] out_any,

output [99:0] out_different

);

// See gatesv for explanations.

assign out_both = in & in[99:1];

assign out_any = in[99:1] | in ;

assign out_different = in ^ {in[0], in[99:1]};

endmodule

// 另一種 方法

module top_module( 

    input [99:0] in,

    output [98:0] out_both,

    output [99:1] out_any,

    output [99:0] out_different );

 /*

    assign out_both = in[99:1] & in[98:0];

    assign out_any = in[99:1] | in[98:0];

    assign out_different = {in[0], in[99:1]} ^ in;

*/

integer i;

    always @(*) begin

        for (i=0;i<=98;i=i+1) begin

            out_both[i] =in[i+1] & in[i];

            out_any[i+1]  =in[i+1] | in[i];

            out_different[i] =in[i+1] ^ in[i];

        end

     end

    assign  out_different[99] =in[99] ^ in[0];

endmodule