HBLbits_Verilog Basic_Exams/2014 q4a
Consider the n-bit shift register circuit shown below:
Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.
module top_module (
input clk,
input w, R, E, L,
output Q
);
always@(posedge clk) begin
case({E,L})
2'b00:Q<=Q;
2'b01:Q<=R;
2'b10:Q<=w;
2'b11:Q<=R;
endcase
end
endmodule
input clk,
input w, R, E, L,
output Q
);
always@(posedge clk) begin
case({E,L})
2'b00:Q<=Q;
2'b01:Q<=R;
2'b10:Q<=w;
2'b11:Q<=R;
endcase
end
endmodule
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