HBLbits_Verilog Basic_Exams/m2014 q4a
Implement the following circuit:
Note that this is a latch, so a Quartus warning about having inferred a latch is expected
module top_module (
input d,
input ena,
output q);
always @(*) begin
if (ena)
q=d;
end
endmodule
input d,
input ena,
output q);
always @(*) begin
if (ena)
q=d;
end
endmodule
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