HBLbits_Verilog Basic_Vector100r
Given a 100-bit input vector [99:0], reverse its bit ordering.
A for loop (in a combinational always block or generate block) would be useful here. I would prefer a combinational always block in this case because module instantiations (which require generate blocks) aren't needed.
module top_module(
input [99:0] in,
output [99:0] out
);
integer i;
always@(*)begin
for(i=0;i<100;i=i+1)begin
out[99-i] = in[i];
end
end
endmodule
input [99:0] in,
output [99:0] out
);
integer i;
always@(*)begin
for(i=0;i<100;i=i+1)begin
out[99-i] = in[i];
end
end
endmodule
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