HBLbits_Verilog Basic_Exams/m2014 q3
Consider the function f shown in the Karnaugh map below.
f = x1' x3 + x2 x4
module top_module (
input [4:1] x,
output f );
//f = x1' x3 + x2 x4
assign f= (x[4]& x[2]) | (x[3]& ~x[1]);
endmodule
2024產專班 作業2 (純模擬) 1) LED ON,OFF,TIMER,FLASH 模擬 (switch 控制) 2)RFID卡號模擬 (buttom 模擬RFID UID(不從ESP32) Node-Red 程式 [{"id":"d8886...
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