HDLBits — Verilog Practice

 HDLBits — Verilog Practice

HDLBits is a collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL). Earlier problems follow a tutorial style, while later problems will increasingly challenge your circuit design skills.

Each problem requires you to design a small circuit in Verilog. HDLBits gives you immediate feedback on the circuit module you submit. Your circuit is checked for correctness by simulating with a set of test vectors and comparing it to our reference solution.

How to use HDLBits

1. Choose a problem: Browse the problem set or go to the first problem
2. Write a solution in Verilog
3. Submit, simulate, and debug if necessary

If you want to track your progress or move to another browser, create a username and password so you can log in from elsewhere.

Which exercises should I do?

The exercises are organized by topic and by approximately difficulty within each topic. Start first with the "Getting Started" section to get familiar with how to use HDLBits. Then start with the easier problems of each topic, and not in a strict top-to-bottom order. The "Verilog Language" section focuses more on using the Verilog syntax and language features, while the "Circuits" section focuses more on using Verilog to create circuits, so problems from these two categories should be done concurrently (practicing new language features while the circuits you create become more complex).

Topics

Getting Started

Using HDLBits

Verilog Language

Problems that focus on introducing Verilog language syntax and features.

Combinational Logic

Logic gates, modules, vectors, combinational always blocks, k-maps, ...

Sequential Logic

Flip-flops, counters, shift registers, finite-state machines

Reading Simulations

Finding bugs, creating circuits from waveforms.

Writing Testbenches

Writing non-synthesizable Verilog testbenches

Run a Simulation

You can run Verilog simulations using our web interface for Icarus Verilog. This is useful for creating shareable simulations of short bits of Verilog.