HBLbits_Verilog Basic_Exams/m2014 q4e
Implement the following circuit:
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
WOKWI DHT22 & LED , Node-Red + SQLite database Node-Red程式 [{"id":"6f0240353e534bbd","type":"comment&...
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