HBLbits_Verilog Basic_Exams/m2014 q4g
Implement the following circuit:
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = ~(in1 ^in2) ^ in3 ;
endmodule
input in1,
input in2,
input in3,
output out);
assign out = ~(in1 ^in2) ^ in3 ;
endmodule
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