HBLbits_Verilog Basic_Kmap3
Implement the circuit described by the Karnaugh map below.
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~((~a & ~c) | (~c&d) | (~a&b));
endmodule
input a,
input b,
input c,
input d,
output out );
assign out = ~((~a & ~c) | (~c&d) | (~a&b));
endmodule
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