HBLbits_Verilog Basic_Dff8
Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
q <=d;
end
endmodule
input clk,
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
q <=d;
end
endmodule
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