HBLbits_Verilog Basic_Mux2to1v
Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
always @(*) begin
case (sel)
1'b0: out = a;
1'b1: out = b;
endcase
end
endmodule
input sel,
output [99:0] out );
always @(*) begin
case (sel)
1'b0: out = a;
1'b1: out = b;
endcase
end
endmodule
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