2016年6月3日 星期五

State Machines

源自於  http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.html


State Machines


XST proposes a large set of templates to describe Finite State Machines (FSMs). By default, XST tries to recognize FSMs from VHDL/Verilog code, and apply several state encoding techniques (it can re-encode the user's initial encoding) to get better performance or less area. However, you can disable FSM extraction using a FSM_extract design constraint.
Please note that XST can handle only synchronous state machines.
There are many ways to describe FSMs. A traditional FSM representation incorporates Mealy and Moore machines, as in the following figure:

For HDL, process (VHDL) and always blocks (Verilog) are the most suitable ways for describing FSMs. (For description convenience Xilinx uses "process" to refer to both: VHDL processes and Verilog always blocks).
You may have several processes (1, 2 or 3) in your description, depending upon how you consider and decompose the different parts of the preceding model. Following is an example of the Moore Machine with Asynchronous Reset, "RESET".
  • 4 states: s1, s2, s3, s4
  • 5 transitions
  • 1 input: "x1"
  • 1 output: "outp"
This model is represented by the following bubble diagram:

Related Constraints

Related constraints are:
  • FSM_extract
  • FSM_encoding
  • FSM_fftype
  • ENUM_encoding

FSM with 1 Process

Please note, in this example output signal "outp" is a register.

VHDL

Following is the VHDL code for an FSM with a single process.
library IEEE;  
use IEEE.std_logic_1164.all; 
 
entity fsm is  
  port ( clk, reset, x1 : IN std_logic;  
                  outp : OUT std_logic);  
end entity;  
architecture beh1 of fsm is 
  type state_type is (s1,s2,s3,s4);  
  signal state: state_type ;  
begin  
  process (clk,reset)  
  begin  
    if (reset ='1') then  
      state <=s1; outp<='1';  
    elsif (clk='1' and clk'event) then  
      case state is  
        when s1 => if x1='1' then state <= s2;  
                    else          state <= s3;  
                    end if;  
                    outp <= '1';  
        when s2 => state <= s4; outp <= '1';  
        when s3 => state <= s4; outp <= '0';  
        when s4 => state <= s1; outp <= '0'; 
      end case;  
    end if;  
  end process;  
end beh1; 

Verilog

Following is the Verilog code for an FSM with a single process.
module fsm (clk, reset, x1, outp);  
  input clk, reset, x1;  
  output outp;  
  reg outp; 
 
reg [1:0] state;  
parameter s1 = 2'b00; parameter s2 = 2'b01;  
parameter s3 = 2'b10; parameter s4 = 2'b11; 
 
  always@(posedge clk or posedge reset)  
  begin  
    if (reset)  
      begin  
        state = s1; outp = 1'b1;  
      end  
    else  
      begin  
        case (state)  
          s1: begin  
                if (x1==1'b1) state = s2;  
                else          state = s3;  
                outp = 1'b1;  
              end  
          s2: begin  
                state = s4; outp = 1'b1;  
              end  
          s3: begin  
                state = s4; outp = 1'b0;  
              end  
          s4: begin  
                state = s1; outp = 1'b0;  
              end  
        endcase  
      end  
  end  
endmodule 

FSM with 2 Processes

To eliminate a register from the "outputs", you can remove all assignments "outp <=..." from the Clock synchronization section.
This can be done by introducing two processes as shown in the following figure.

VHDL

Following is VHDL code for an FSM with two processes.
library IEEE;  
use IEEE.std_logic_1164.all; 
 
entity fsm is  
  port ( clk, reset, x1 : IN std_logic;  
                  outp : OUT std_logic);  
end entity;  
architecture beh1 of fsm is  
  type state_type is (s1,s2,s3,s4);  
  signal state: state_type ;  
begin  
  process1: process (clk,reset)  
  begin  
    if (reset ='1') then state <=s1;  
    elsif (clk='1' and clk'Event) then  
      case state is  
        when s1 => if x1='1' then state <= s2;  
                    else           state <= s3;  
                    end if;  
        when s2 => state <= s4;  
        when s3 => state <= s4;  
        when s4 => state <= s1;  
      end case;  
    end if;  
  end process process1;  
 
process2 : process (state)  
  begin  
    case state is  
      when s1 => outp <= '1';  
      when s2 => outp <= '1';  
      when s3 => outp <= '0';  
      when s4 => outp <= '0';  
    end case;  
end process process2;  
end beh1; 

Verilog

Following is the Verilog code for an FSM with two processes.
module fsm (clk, reset, x1, outp);  
  input clk, reset, x1;  
  output outp;  
  reg outp; 
 
reg [1:0] state;  
parameter s1 = 2'b00; parameter s2 = 2'b01;  
parameter s3 = 2'b10; parameter s4 = 2'b11; 
 
  always @(posedge clk or posedge reset)  
  begin  
    if (reset)  
      state = s1;  
    else  
      begin  
        case (state)  
          s1: if (x1==1'b1) state = s2;  
              else          state = s3;  
          s2: state = s4;  
          s3: state = s4;  
          s4: state = s1;  
        endcase  
      end  
  end  
 
  always @(state)  
  begin  
        case (state)  
          s1: outp = 1'b1;  
          s2: outp = 1'b1;  
          s3: outp = 1'b0;  
          s4: outp = 1'b0;   
        endcase  
  end  
endmodule 

FSM with 3 Processes

You can also separate the NEXT State function from the State Register:

Separating the NEXT State function from the State Register provides the following description:

VHDL

Following is the VHDL code for an FSM with three processes.
library IEEE;  
use IEEE.std_logic_1164.all; 
 
entity fsm is  
  port ( clk, reset, x1 : IN std_logic;  
                    outp : OUT std_logic);  
end entity;  
architecture beh1 of fsm is  
  type state_type is (s1,s2,s3,s4);  
  signal state, next_state: state_type ;  
begin 
  process1: process (clk,reset)  
  begin  
    if (reset ='1') then  
      state <=s1;  
    elsif (clk='1' and clk'Event) then  
      state <= next_state;  
    end if;  
  end process process1; 
 
  process2 : process (state, x1)  
  begin  
    case state is  
          when s1 => if x1='1' then   
                        next_state <= s2;  
                      else  
                        next_state <= s3;  
                      end if;  
          when s2 => next_state <= s4;  
          when s3 => next_state <= s4;  
          when s4 => next_state <= s1;  
    end case;  
end process process2; 
 
process3 : process (state)  
  begin  
      case state is  
          when s1 => outp <= '1';  
          when s2 => outp <= '1';  
          when s3 => outp <= '0';  
          when s4 => outp <= '0';  
      end case;  
end process process3;  
end beh1; 

Verilog

Following is the Verilog code for an FSM with three processes.
module fsm (clk, reset, x1, outp);  
  input clk, reset, x1;  
  output outp;  
  reg outp;  
 
reg [1:0] state;  
reg [1:0] next_state;  
parameter s1 = 2'b00; parameter s2 = 2'b01;  
parameter s3 = 2'b10; parameter s4 = 2'b11; 
 
  always @(posedge clk or posedge reset)  
  begin  
    if (reset)  state = s1;  
    else        state = next_state;  
  end 
 
  always @(state or x1)  
  begin  
        case (state)  
          s1: if (x1==1'b1) next_state = s2;  
              else          next_state = s3;  
          s2: next_state = s4;   
          s3: next_state = s4;   
          s4: next_state = s1;   
        endcase  
  end 
 
  always @(state)  
  begin  
        case (state)  
          s1: outp = 1'b1;  
          s2: outp = 1'b1;  
          s3: outp = 1'b0;  
          s4: outp = 1'b0;   
        endcase  
  end  
endmodule 

State Registers

State Registers must to be initialized with an asynchronous or synchronous signal. XST does not support FSM without initialization signals. Please refer to the "Registers" section of this chapter for templates on how to write Asynchronous and Synchronous initialization signals.
In VHDL the type of a state register can be a different type: integer, bit_vector, std_logic_vector, for example. But it is common and convenient to define an enumerated type containing all possible state values and to declare your state register with that type.
In Verilog, the type of state register can be an integer or a set of defined parameters. In the following Verilog examples the state assignments could have been made like this:
parameter [3:0] 
  s1 = 4'b0001, 
  s2 = 4'b0010, 
  s3 = 4'b0100, 
  s4 = 4'b1000; 
reg [3:0] state; 
These parameters can be modified to represent different state encoding schemes.

Next State Equations

Next state equations can be described directly in the sequential process or in a distinct combinational process. The simplest template is based on a Case statement. If using a separate combinational process, its sensitivity list should contain the state signal and all FSM inputs.

FSM Outputs

Non-registered outputs are described either in the combinational process or concurrent assignments. Registered outputs must be assigned within the sequential process.

FSM Inputs

Registered inputs are described using internal signals, which are assigned in the sequential process.

State Encoding Techniques

XST supports the following state encoding techniques.
  • Auto
  • One-Hot
  • Gray
  • Compact
  • Johnson
  • Sequential
  • User

Auto

In this mode XST tries to select the best suited encoding algorithm for each FSM.

One-Hot

One-hot encoding is the default encoding scheme. Its principle is to associate one code bit and also one flip-flop to each state. At a given clock cycle during operation, one and only one state variable is asserted. Only two state variables toggle during a transition between two states. One-hot encoding is very appropriate with most FPGA targets where a large number of flip-flops are available. It is also a good alternative when trying to optimize speed or to reduce power dissipation.

Gray

Gray encoding guarantees that only one state variable switches between two consecutive states. It is appropriate for controllers exhibiting long paths without branching. In addition, this coding technique minimizes hazards and glitches. Very good results can be obtained when implementing the state register with T flip-flops.

Compact

Compact encoding, consists of minimizing the number of state variables and flip-flops. This technique is based on hypercube immersion. Compact encoding is appropriate when trying to optimize area.

Johnson

Like Gray, Johnson encoding shows benefits with state machines containing long paths with no branching.

Sequential

Sequential encoding consists of identifying long paths and applying successive radix two codes to the states on these paths. Next state equations are minimized.

User

In this mode, XST uses original encoding, specified in the HDL file. For example, if you use enumerated types for a state register, then in addition you can use the enum_encoding constraint to assign a specific binary value to each state. Please refer to the "Design Constraints" chapter for more details.

Finite State Machine (FSM) Coding In VHDL

--源自於http://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.html

Finite State Machine (FSM) Coding In VHDL

There is a special Coding style for State Machines in VHDL as well as in Verilog.
Let us consider below given state machine which is a “1011” overlapping sequence
detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains
 ‘0’ for other states.



--------------------------------------
---VHDL Code for FSM:
--------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 
--Sequence detector for detecting the sequence "1011".
--Overlapping type.
entity FSM1 is
port(   
        clk   : in std_logic;      --clock signal
        reset : in std_logic;      --reset signal
        S_in  : in std_logic;      --serial bit Input sequence    
        S_out : out std_logic);    -- Output         
end FSM1;
--------------------------------------
architecture Behavioral of FSM1 is 
--Defines the type for states in the state machine

type state_type is (S0,S1,S2,S3,S4); 
--Declare the signal with the corresponding state type.

signal Current_State, Next_State : state_type; 

begin 
-- Synchronous Process
process(clk) 
begin
    if( reset = '1' ) then                 --Synchronous Reset
        Current_State <= 'S0'; 
    elsif (clk'event and clk = '1') then   --Rising edge of Clock
        Current_State <= Next_State
    end if;
end process; 

-- Combinational Process
Process(Current_State, S_in)
    begin
        case Current_State is 
            when S0 =>             -- in:0--> S0,in:1-->S1       
                S_out <= '0';
                if ( s_in = '0' ) then
                    Next_State <= S0;
                else    
                    Next_State <= S1;
                end if; 
            when S1 =>             -- in:0--> S3,in:1-->S2  
                S_out <= '1';   
                if ( S_in = '0' ) then
                    Next_State <= S3;
                else    
                    Next_State <= S2;
                end if; 
            when S2 =>            -- in:0--> S0,in:1-->S3  
                S_out <= '0';   
                if ( S_in = '0' ) then
                    Next_State <= S0;
                else    
                    Next_State <= S3;
                end if; 
            when S3 =>             -- in:0--> S2,in:1-->S4  
                S_out <= '1';   
                if (S_in = '0' ) then
                    Next_State <= S2;
                else    
                    Next_State <= S4;
                end if; 
            when S4 =>             -- in:0--> S2,in:1-->S1  
                S_out <= '1';   
                if ( S_in = '0' ) then
                    Next_State <= S2;
                else    
                    Next_State <= S1;
                end if; 
            when others =>
                NULL;
        end case;
        
        
    end if;
end process;    

具有預載Preload 與 計數致能count enable的 2進制Binary計數器

具有預載Preload 與 計數致能count enable的 2進制Binary計數器

輸入 : DIP SW  Data[7..0]
              預載Preload
                 clk ---clock
,up_down ---up / down counter
,ena                ---enable counter
,load : in std_logic; --load 8-bit Data in 
data_in : in std_logic_vector(7 downto 0); --Data in
輸出       d0,d1七段顯示器 靜態方式  共陰極
           : out std_logic_vector(6 downto 0) ---7-segment digit0 digit1





------------------------------------------
--with Preload & Enable 8 bit Counter
--input : Clock 48Mhz divide into 1Hz
--output : 2 digits 7-segment
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
------------------------------------------
entity Preload_CNT is
port(
clk ---clock
,up_down ---up / down counter
,ena ---enable counter
,load : in std_logic; --load 8-bit Data in 
data_in : in std_logic_vector(7 downto 0); --Data in
d0,d1 : out std_logic_vector(6 downto 0) ---7-segment digit0 digit1
);
end Preload_CNT;
------------------------------------------
architecture arch_count of Preload_CNT is 

signal s0,s1: std_logic_vector (6 downto 0);
signal cnt : std_logic_vector(7 downto 0);
signal freq1: integer range 0 to 23999999 := 0;
signal hz1 : std_logic := '0'; 

----------------------------------------------
component seg_d7 is
port(
     bin : in std_logic_vector(3 downto 0);
     seg7: out std_logic_vector(6 downto 0)
     );
end component;

------------------------------------------
begin
------------------------------------------
Clk_generator: 
process (clk)
  begin 
    if(clk'event and clk = '1') then
if(freq1 >= 23999999) then 
                freq1 <= 0;
                hz1 <= not hz1;
        else
                freq1 <= freq1 + 1;
        end if;
    end if;
end process ;
------------------------------------------    
Count_process: 
process (hz1)
variable dir : integer ;
begin
if (up_down='1') then
dir:=1 ; ----up counter
else
dir:=-1 ; ----down counter
end if;
    --------------------------
    if(hz1'event and hz1 = '1') then 
   if (load='1') then  -----load data
cnt <= data_in ;
  elsif  (ena='1') then  -----enable counter active
cnt <= cnt + dir ; ---up / down counter dir=1 /-1
        end if;
    end if;
    
 end process;      

------------------------------------------   
    u1:seg_d7 port map(cnt(7 downto 4),d1);

    u0:seg_d7 port map(cnt(3 downto 0),d0);
------------------------------------------       

end arch_count;

----------------------------------------------------------------
---------------------------------------------
--Binary to 7segment
--7segment--> Common cathodee 7-segment display
----a,b,c,d,e,f,g---
---------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY seg_d7 IS
PORT(
bin : in std_logic_vector(3 downto 0);
seg7 : out std_logic_vector(6 downto 0)
);
END seg_d7;

ARCHITECTURE arch_seg_d7  OF seg_d7 IS
BEGIN --a,b,c,d,e,f,g---
seg7 <= "1111110" when bin="0000" else
"0110000" when bin="0001" else
"1101101" when bin="0010" else
"1111001" when bin="0011" else
"0110011" when bin="0100" else
"1011011" when bin="0101" else
"1011111" when bin="0110" else
"1110000" when bin="0111" else
"1111111" when bin="1000" else
"1111011" when bin="1001" else
"1110111" when bin="1010" else
"0011111" when bin="1011" else
"1001110" when bin="1100" else
"0111101" when bin="1101" else
"1001111" when bin="1110" else
"1000111" when bin="1111" else
"0000000";
--seg7 <= "0000001" when bin="0000" else
-- "1001111" when bin="0001" else
-- "0010010" when bin="0010" else
-- "0000110" when bin="0011" else
-- "1001100" when bin="0100" else
-- "0100100" when bin="0101" else
-- "0100000" when bin="0110" else
-- "0001111" when bin="0111" else
-- "0000000" when bin="1000" else
-- "0000100" when bin="1001" else
-- "0001000" when bin="1010" else
-- "1100000" when bin="1011" else
-- "0110001" when bin="1100" else
-- "1000010" when bin="1101" else
-- "0110000" when bin="1110" else
-- "0111000" when bin="1111" else
-- "1111111";
END arch_seg_d7 ;


----------------------------------------------------------------
To Direction Location I/O Bank
clk Input PIN_21 1
d0[6] Output PIN_37 4
d0[5] Output PIN_39 4
d0[4] Output PIN_41 4
d0[3] Output PIN_43 4
d0[2] Output PIN_45 4
d0[1] Output PIN_49 4
d0[0] Output PIN_51 4
d1[6] Output PIN_57 4
d1[5] Output PIN_59 4
d1[4] Output PIN_61 4
d1[3] Output PIN_63 4
d1[2] Output PIN_67 4
d1[1] Output PIN_69 4
d1[0] Output PIN_71 4
data_in[7] Input PIN_15 1
data_in[6] Input PIN_13 1
data_in[5] Input PIN_11 1
data_in[4] Input PIN_7 1
data_in[3] Input PIN_5 1
data_in[2] Input PIN_3 1
data_in[1] Input PIN_1 1
data_in[0] Input PIN_143 2
ena Input PIN_31 1
load Input PIN_29 1
up_down Input PIN_32 1

2016年6月1日 星期三

VHDL BCD counter 0000-9999

VHDL BCD counter 0000-9999




--------------------------------------------------------------------
---BCD 9999 counter 
--------------------------------------------------------------------
-------------dp,g,f,e,d,c,b,a--------------
-------------diplay_ou[6....0]
-------------------------------------------
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 


entity BCD_CNT_9999 is 

   Port ( 
 clk : in  STD_LOGIC; 
          reset : in  STD_LOGIC; 
          display_control : out  STD_LOGIC_vector(3 downto 0); 
 display_out : out  STD_LOGIC_vector(6 downto 0)); 

end BCD_CNT_9999; 

architecture Behavioral of BCD_CNT_9999 is 
--local signal declaration 
signal count:std_logic_vector(25 downto 0); 

signal bcd_out1:std_logic_vector(3 downto 0); 
signal bcd_out2:std_logic_vector(3 downto 0); 
signal bcd_out3:std_logic_vector(3 downto 0); 
signal bcd_out4:std_logic_vector(3 downto 0); 

signal clk_4hz:std_logic; 
signal tc1:std_logic; 
signal tc2:std_logic; 
signal tc3:std_logic; 

-- component declaration 
component mux_display is 
port(

clk,reset:in std_logic;
dis1:in std_logic_vector(3 downto 0); 
dis2:in std_logic_vector(3 downto 0); 
dis3:in std_logic_vector(3 downto 0); 
dis4:in std_logic_vector(3 downto 0); 

display_control:out std_logic_vector(3 downto 0); 
display:out std_logic_vector(6 downto 0)); 
end component; 
  
begin 
 -- This process divides the system clock of 48-mhz, to scale it down to 4hz. 
process(clk,reset)
 begin 
if reset='1' then 
count<="00000000000000000000000000"; 
elsif clk'event and clk='1' then 
count <= count+'1'; 
if count >=23999999 then 
count<="00000000000000000000000000"; 
end if;
end if; 
end process; 

clk_4hz <= count(23);   ----------  2^6 * 2^20Hz
---------- ================  = 4 Hz
----------  2^4 * 2^20Hz

--process for first BCD counter 

process(clk_4hz,reset) 
begin 
     if reset='1' then 
bcd_out1 <= "0000"; 
elsif clk_4hz='1' and clk_4hz'event then 
if bcd_out1="1001" then 
bcd_out1 <= "0000"; 
else 
bcd_out1 <= bcd_out1+'1'; 
end if; 
 end if; 
 end process; 
  
 tc1 <='0' when bcd_out1="1001" else '1'; 
  

--process for second BCD counter 

process(tc1,reset) 
begin 
if reset='1' then 
bcd_out2 <= "0000"; 
elsif tc1'event and tc1 ='1'  then 
if bcd_out2="1001" then 
bcd_out2 <= "0000"; 
else 
bcd_out2 <= bcd_out2+'1'; 
end if; 
end if; 
end process; 

tc2<='0' when bcd_out2="1001"else '1'; 


--process for third BCD counter 

process(tc2,reset) 
begin 
if reset='1' then 
bcd_out3 <= "0000"; 
elsif tc2'event and tc2='1'  then 
if bcd_out3   =   "1001" then 
bcd_out3 <= "0000"; 
else 
bcd_out3 <= bcd_out3+'1'; 
end if; 
end if; 
end process; 

tc3<='0' when bcd_out3 = "1001" else  '1'; 
  
--process for fourth BCD counter 
process(tc3,reset) 
begin 
if reset='1' then 
bcd_out4 <= "0000"; 
elsif  tc3'event and tc3='1' then 
if bcd_out4 = "1001" then 
bcd_out4 <= "0000"; 
else 
bcd_out4 <= bcd_out4+'1'; 
end if; 
end if; 
end process; 

--component instantiation 
u1:mux_display 
port map (
clk     => clk, 
reset => reset, 
dis1 => bcd_out1, 
dis2 => bcd_out2, 
dis3 => bcd_out3, 
dis4 => bcd_out4, 
display => display_out, 
display_control   => display_control); 

end Behavioral; 



------------------------------------------------------------------------- 
---clock 48Mhz 9999 BCD Counter
------------------------------------------------------------------------- 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity mux_display is 
   Port ( clk,reset : in  STD_LOGIC; 
          dis1 : in  STD_LOGIC_VECTOR(3 downto 0); 
          dis2 : in  STD_LOGIC_VECTOR(3 downto 0); 
          dis3 : in  STD_LOGIC_VECTOR(3 downto 0); 
          dis4 : in  STD_LOGIC_VECTOR(3 downto 0); 
          display_control : out  STD_LOGIC_VECTOR(3 downto 0); 
          display : out  STD_LOGIC_VECTOR(6 downto 0)); 
end mux_display; 

architecture Behavioral of mux_display is 
signal count2 : STD_LOGIC_VECTOR(11 downto 0); 
signal dis: STD_LOGIC_VECTOR(3 downto 0); 
signal count_2bit: STD_LOGIC_VECTOR(1 downto 0); 
signal clk_4khz: std_logic; 

begin 


--This process divides the system clock of 4-mhz, to scale it down to 4khz. 
--for multiplxing 

   process(clk,reset) 
     begin 
       if reset='1' then 
         count2<="000000000000"; 
       elsif clk'event and clk='1'  then 
         count2<= count2+'1'; 
       end if; 
    end process; 
  
  clk_4khz<= count2(11); 
  

--process for 2 bit counter operated on clock of 4khz 

process(clk_4khz,reset) 
   begin 
if reset='1' then 
count_2bit<="00"; 
elsif clk_4khz'event and clk_4khz='1' then 
count_2bit<= count_2bit+'1'; 
end if; 
end process; 

dis <= dis1 when count_2bit="00" else 
        dis2 when count_2bit="01" else 
        dis3 when count_2bit="10" else 
        dis4; 

display_control <= "0001" when count_2bit="00" else 
"0010" when count_2bit="01" else 
"0100" when count_2bit="10" else 
"1000"; 
-------------------------------------------
-------------dp,g,f,e,d,c,b,a--------------
-------------------------------------------
display <=  "1000000" when dis="0000" else 
"1111001" when dis="0001" else 
"0100100" when dis="0010" else 
"0110000" when dis="0011" else 
"0011001" when dis="0100" else 
"0010010" when dis="0101" else 
"0000010" when dis="0110" else 
"1111000" when dis="0111" else 
"0000000" when dis="1000" else 
"0010000" when dis="1001" else 
"1111111"; --when dis others; 
end Behavioral;



To Direction Location I/O Bank
clk Input PIN_114 2
display_control[3] Output PIN_113 2
display_control[2] Output PIN_111 2
display_control[1] Output PIN_109 2
display_control[0] Output PIN_107 3
display_out[6] Output PIN_86 3
display_out[5] Output PIN_84 3
display_out[4] Output PIN_80 3
display_out[3] Output PIN_78 3
display_out[2] Output PIN_76 3
display_out[1] Output PIN_74 3
display_out[0] Output PIN_72 4
reset Input PIN_108 3





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