VHDL BCD counter 0000-9999
--------------------------------------------------------------------
---BCD 9999 counter
--------------------------------------------------------------------
-------------dp,g,f,e,d,c,b,a--------------
-------------diplay_ou[6....0]
-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_CNT_9999 is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
display_control : out STD_LOGIC_vector(3 downto 0);
display_out : out STD_LOGIC_vector(6 downto 0));
end BCD_CNT_9999;
architecture Behavioral of BCD_CNT_9999 is
--local signal declaration
signal count:std_logic_vector(25 downto 0);
signal bcd_out1:std_logic_vector(3 downto 0);
signal bcd_out2:std_logic_vector(3 downto 0);
signal bcd_out3:std_logic_vector(3 downto 0);
signal bcd_out4:std_logic_vector(3 downto 0);
signal clk_4hz:std_logic;
signal tc1:std_logic;
signal tc2:std_logic;
signal tc3:std_logic;
-- component declaration
component mux_display is
port(
clk,reset:in std_logic;
dis1:in std_logic_vector(3 downto 0);
dis2:in std_logic_vector(3 downto 0);
dis3:in std_logic_vector(3 downto 0);
dis4:in std_logic_vector(3 downto 0);
display_control:out std_logic_vector(3 downto 0);
display:out std_logic_vector(6 downto 0));
end component;
begin
-- This process divides the system clock of 48-mhz, to scale it down to 4hz.
process(clk,reset)
begin
if reset='1' then
count<="00000000000000000000000000";
elsif clk'event and clk='1' then
count <= count+'1';
if count >=23999999 then
count<="00000000000000000000000000";
end if;
end if;
end process;
clk_4hz <= count(23); ---------- 2^6 * 2^20Hz
---------- ================ = 4 Hz
---------- 2^4 * 2^20Hz
--process for first BCD counter
process(clk_4hz,reset)
begin
if reset='1' then
bcd_out1 <= "0000";
elsif clk_4hz='1' and clk_4hz'event then
if bcd_out1="1001" then
bcd_out1 <= "0000";
else
bcd_out1 <= bcd_out1+'1';
end if;
end if;
end process;
tc1 <='0' when bcd_out1="1001" else '1';
--process for second BCD counter
process(tc1,reset)
begin
if reset='1' then
bcd_out2 <= "0000";
elsif tc1'event and tc1 ='1' then
if bcd_out2="1001" then
bcd_out2 <= "0000";
else
bcd_out2 <= bcd_out2+'1';
end if;
end if;
end process;
tc2<='0' when bcd_out2="1001"else '1';
--process for third BCD counter
process(tc2,reset)
begin
if reset='1' then
bcd_out3 <= "0000";
elsif tc2'event and tc2='1' then
if bcd_out3 = "1001" then
bcd_out3 <= "0000";
else
bcd_out3 <= bcd_out3+'1';
end if;
end if;
end process;
tc3<='0' when bcd_out3 = "1001" else '1';
--process for fourth BCD counter
process(tc3,reset)
begin
if reset='1' then
bcd_out4 <= "0000";
elsif tc3'event and tc3='1' then
if bcd_out4 = "1001" then
bcd_out4 <= "0000";
else
bcd_out4 <= bcd_out4+'1';
end if;
end if;
end process;
--component instantiation
u1:mux_display
port map (
clk => clk,
reset => reset,
dis1 => bcd_out1,
dis2 => bcd_out2,
dis3 => bcd_out3,
dis4 => bcd_out4,
display => display_out,
display_control => display_control);
end Behavioral;
-------------------------------------------------------------------------
---clock 48Mhz 9999 BCD Counter
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_display is
Port ( clk,reset : in STD_LOGIC;
dis1 : in STD_LOGIC_VECTOR(3 downto 0);
dis2 : in STD_LOGIC_VECTOR(3 downto 0);
dis3 : in STD_LOGIC_VECTOR(3 downto 0);
dis4 : in STD_LOGIC_VECTOR(3 downto 0);
display_control : out STD_LOGIC_VECTOR(3 downto 0);
display : out STD_LOGIC_VECTOR(6 downto 0));
end mux_display;
architecture Behavioral of mux_display is
signal count2 : STD_LOGIC_VECTOR(11 downto 0);
signal dis: STD_LOGIC_VECTOR(3 downto 0);
signal count_2bit: STD_LOGIC_VECTOR(1 downto 0);
signal clk_4khz: std_logic;
begin
--This process divides the system clock of 4-mhz, to scale it down to 4khz.
--for multiplxing
process(clk,reset)
begin
if reset='1' then
count2<="000000000000";
elsif clk'event and clk='1' then
count2<= count2+'1';
end if;
end process;
clk_4khz<= count2(11);
--process for 2 bit counter operated on clock of 4khz
process(clk_4khz,reset)
begin
if reset='1' then
count_2bit<="00";
elsif clk_4khz'event and clk_4khz='1' then
count_2bit<= count_2bit+'1';
end if;
end process;
dis <= dis1 when count_2bit="00" else
dis2 when count_2bit="01" else
dis3 when count_2bit="10" else
dis4;
display_control <= "0001" when count_2bit="00" else
"0010" when count_2bit="01" else
"0100" when count_2bit="10" else
"1000";
-------------------------------------------
-------------dp,g,f,e,d,c,b,a--------------
-------------------------------------------
display <= "1000000" when dis="0000" else
"1111001" when dis="0001" else
"0100100" when dis="0010" else
"0110000" when dis="0011" else
"0011001" when dis="0100" else
"0010010" when dis="0101" else
"0000010" when dis="0110" else
"1111000" when dis="0111" else
"0000000" when dis="1000" else
"0010000" when dis="1001" else
"1111111"; --when dis others;
end Behavioral;
| To | Direction | Location | I/O Bank |
| clk | Input | PIN_114 | 2 |
| display_control[3] | Output | PIN_113 | 2 |
| display_control[2] | Output | PIN_111 | 2 |
| display_control[1] | Output | PIN_109 | 2 |
| display_control[0] | Output | PIN_107 | 3 |
| display_out[6] | Output | PIN_86 | 3 |
| display_out[5] | Output | PIN_84 | 3 |
| display_out[4] | Output | PIN_80 | 3 |
| display_out[3] | Output | PIN_78 | 3 |
| display_out[2] | Output | PIN_76 | 3 |
| display_out[1] | Output | PIN_74 | 3 |
| display_out[0] | Output | PIN_72 | 4 |
| reset | Input | PIN_108 | 3 |
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