--源自於http://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.html
Finite State Machine (FSM) Coding In VHDL
There is a special Coding style for State Machines in VHDL as well as in Verilog.
Let us consider below given state machine which is a “1011” overlapping sequence
detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains
‘0’ for other states.
detector. Output becomes ‘1’ when sequence is detected in state S4 else it remains
‘0’ for other states.
--------------------------------------
---VHDL Code for FSM:
--------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Sequence detector for detecting the sequence "1011".
--Overlapping type.
entity FSM1 is
port(
clk : in std_logic; --clock signal
reset : in std_logic; --reset signal
S_in : in std_logic; --serial bit Input sequence
S_out : out std_logic); -- Output
end FSM1;
--------------------------------------
architecture Behavioral of FSM1 is
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
begin
-- Synchronous Process
process(clk)
begin
if( reset = '1' ) then --Synchronous Reset
Current_State <= 'S0';
elsif (clk'event and clk = '1') then --Rising edge of Clock
Current_State <= Next_State
end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
begin
case Current_State is
when S0 => -- in:0--> S0,in:1-->S1
S_out <= '0';
if ( s_in = '0' ) then
Next_State <= S0;
else
Next_State <= S1;
end if;
when S1 => -- in:0--> S3,in:1-->S2
S_out <= '1';
if ( S_in = '0' ) then
Next_State <= S3;
else
Next_State <= S2;
end if;
when S2 => -- in:0--> S0,in:1-->S3
S_out <= '0';
if ( S_in = '0' ) then
Next_State <= S0;
else
Next_State <= S3;
end if;
when S3 => -- in:0--> S2,in:1-->S4
S_out <= '1';
if (S_in = '0' ) then
Next_State <= S2;
else
Next_State <= S4;
end if;
when S4 => -- in:0--> S2,in:1-->S1
S_out <= '1';
if ( S_in = '0' ) then
Next_State <= S2;
else
Next_State <= S1;
end if;
when others =>
NULL;
end case;
end if;
end process;
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