HBLbits_Verilog Basic_Exams/m2014 q4c

HBLbits_Verilog Basic_Exams/m2014 q4c 

Implement the following circuit:

input r,   // synchronous reset 同步式Reset

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
	always@(posedge clk) begin
        if (r)
            q<=0;
        else
            q<=d;
    end
endmodule