HBLbits_Verilog Basic_Exams/m2014 q4b
Implement the following circuit:
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always@(posedge clk or posedge ar) begin
if (ar)
q<=0;
else
q<=d;
end
endmodule
input clk,
input d,
input ar, // asynchronous reset
output q);
always@(posedge clk or posedge ar) begin
if (ar)
q<=0;
else
q<=d;
end
endmodule
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