HBLbits_Verilog Basic_Fsm1

 HBLbits_Verilog Basic_Fsm1

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1s, but using asynchronous reset.

module top_module (
input clk,
input in,
input areset,
output out
);

parameter A=0, B=1;
reg state; // Ensure state and next are big enough to hold the state encoding.
reg next;
    
    // A finite state machine is usually coded in three parts:
    //   State transition logic
    //   State flip-flops
    //   Output logic
    // It is sometimes possible to combine one or more of these blobs of code
    // together, but be careful: Some blobs are combinational circuits, while some
    // are clocked (DFFs).
     // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.
    always@(*) begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
    end
   
    // Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
    always @(posedge clk, posedge areset) begin
if (areset) state <= B; // Reset to state B
        else state <= next; // Otherwise, cause the state to transition
end
// Combinational output logic. In this problem, an assign statement is the simplest.
// In more complex circuits, a combinational always block may be more suitable.
assign out = (state==B);
endmodule

//另一方法

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  
    parameter A=0, B=1; 
    reg curr_state, next_state;
   
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if (areset) 
            curr_state<=B;
        else 
            curr_state<=next_state;
    end
    always @(*) begin    // This is a combinational always block
        // State transition logic
           case(curr_state)
               A:  begin
                    if (in==0) 
                    next_state=B ;
                    else 
                      next_state=A;
                end
               B:  begin
                    if (in==0) 
                    next_state=A ;
                    else 
                      next_state=B;
                end
           endcase
                    
end
    // Output logic
    // assign out = (state == ...);
always@(*)
begin
    case (curr_state)
        A: out = 1'b0;
        B: out = 1'b1;
    endcase
    end        
endmodule

//另一方法

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  
    parameter A=0, B=1; 
    reg state, next_state;
    always @(*) begin    // This is a combinational always block
        // State transition logic
        case (state)
            A: begin
                if (in==1)
                next_state<=A;
            else
                  next_state<=B;
            end
            B: begin
                if (in==1)
                next_state<=B;
            else
                  next_state<=A;
            end
              
        endcase    
    end
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if (areset)
            state <=B;
        else
            state <=next_state;
    end
    // Output logic
    // assign out = (state == ...);
    assign out = (state==A)?0:1;
endmodule