HBLbits_Verilog Basic_Module pos
module mod_a ( output, output, input, input, input, input );
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
//mod_a (output,output,input,input,input,input );
mod_a inst1 ( out1,out2,a,b,c,d);
endmodule
input a,
input b,
input c,
input d,
output out1,
output out2
);
//mod_a (output,output,input,input,input,input );
mod_a inst1 ( out1,out2,a,b,c,d);
endmodule
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