Verilog Positive Edge Detector

module pos_edge_det (sig,clk,pe);
  
input sig;           
// Input signal for which positive edge has to be detected
input clk;            
// Input signal for clock
output pe;           
// Output signal that gives a pulse when a positive edge occurs

reg   sig_dly;  
// Internal signal to store the delayed version of signal

// This always block ensures that sig_dly is exactly 1 clock behind sig
  always @ (posedge clk) begin
    sig_dly <= sig;
  end

    // Combinational logic where sig is AND with delayed, inverted version of sig
    // Assign statement assigns the evaluated expression in the RHS to the internal net pe
  assign pe = sig & ~sig_dly;  
            
endmodule 

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
  reg sig;         // Declare internal TB signal called sig to drive the sig pin of the design
  reg clk;         // Declare internal TB signal called clk to drive clock to the design

  // Instantiate the design in TB and connect with signals in TB
  pos_edge_det UUT(  
.sig(sig),           
.clk(clk),
                .pe(pe));

  // Generate a clock of 100MHz
  always #5 clk = ~clk;           

  // Drive stimulus to the design
  initial begin
    clk <= 0;
    sig <= 0;
    #15 sig <= 1;
    #20 sig <= 0;
    #15 sig <= 1;
    #10 sig <= 0;
    #20 
$stop;
  end  
endmodule