//------------------------------------
// 1-2 DeMux (Gate Level)
// Filename: DeMux_1x2.v
//------------------------------------
module DeMux_1x2(D,S,Y);
input D,S;
output [1:0]Y;
wire s_bar;
not u1(s_bar,S);
and U2(Y[0],s_bar,D);
and U3(Y[1],S,D);
endmodule
//==================================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module TB;
/*
module DeMux_1x2(D,S,Y);
input D,S;
output [1:0]Y;
*/
reg D,S;
wire [1:0] Y;
integer i;
DeMux_1x2 UUT(D,S,Y);
initial begin
for ( i=0;i<=3;i=i+1)
begin
{D,S} = i;
#1;
end
end
endmodule
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