8-bit synchronous counter wit asynchronous reset

8-bit synchronous counter wit asynchronous reset

Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2n-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.

An example of this is given as.

•   3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)
•   4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
•   8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)
• and so on..

The Modulo number can be increased by adding more flip-flops to the counter and cascading is a method of achieving higher modulus counters. Then the modulo or MOD number can simply be written as: MOD number = 2n

4-bit Modulo-16 Counter

Multi-bit asynchronous counters connected in this manner are also called “Ripple Counters” or ripple dividers because the change of state at each stage appears to “ripple” itself through the counter from the LSB output to its MSB output connection. Ripple counters are available in standard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built in clock oscillator and produce excellent frequency division of the fundamental frequency.

//--------------------------------------------------

// 8-bit synchronous counter wit asynchronous reset

//--------------------------------------------------

module CNT_8bit(CLK, RESET, COUNT);

    input CLK;

    input RESET;

    output [7:0] COUNT;

    reg [7:0] COUNT;

always @(posedge CLK or posedge RESET)

begin

   if (RESET)

      COUNT <= 8'b0;

   else 

      COUNT <= COUNT + 1;

end

endmodule

//=====================================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module CNT_8bit(CLK, RESET, COUNT);

    input CLK;

    input RESET;

    output [7:0] COUNT;

*/

// Inputs

    reg CLK;

    reg RESET;

// Outputs

    wire [7:0] COUNT;

// Bidirs

initial

    $monitor($time, "    COUNT = %d     RESET = %b", COUNT[7:0], RESET);

// Instantiate the UUT

    CNT_8bit uut (

        .CLK(CLK), 

        .RESET(RESET), 

        .COUNT(COUNT)

        );

// Stimulate the RESET signal

initial begin

   RESET = 1'b1;

   #45 RESET = 1'b0;

   #200 RESET = 1'b1;

   #50 RESET = 1'b0;

end

// Set up the clock to toggle every 100 time units

initial begin

     CLK = 1'b0;

forever #10 CLK=~CLK;

end

//Finish the simulation at time 400

initial begin

     #6400 $finish;

end

endmodule