Clock Divide by even number 2N (MOD 10)

 Clock Divide by even number 2N (MOD 10)

//============================
module Mod_10  
#( 
parameter WIDTH = 3, // Width of the register required
parameter N = 10 // We will divide by 10 for example in this case
)

(clk,reset, clk_out);

input clk;
input reset;
output clk_out;

reg [WIDTH-1:0] r_reg;
wire [WIDTH-1:0] r_nxt;
reg clk_track;

always @(posedge clk or posedge reset)

begin
  if (reset)
     begin
        r_reg <= 0;
clk_track <= 1'b0;
     end

  else if (r_nxt == (N/2))
     begin
     r_reg <= 0;
     clk_track <= ~clk_track;
   end

  else 
      r_reg <= r_nxt;
end

 assign r_nxt = r_reg+1;          
 assign clk_out = clk_track;

endmodule

//============================

// 時間單位 1ns, 時間精確度1 ps

`timescale 100ns/10ps

module TB_clkdiv2n;

  //input

  reg clk,reset;

    //output 

  wire clk_out;

  Mod_10 UUT (clk,reset,clk_out);

  initial

     clk= 1'b0; 

  always

     #5  clk=~clk; 

  initial

     begin

       #2  reset=1'b1;

       #10 reset=1'b0;

       #500 $stop;

     end

   initial

       $monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);

endmodule