BCD TO 2421 Behavioral Level in Verilog

BCD TO 2421 Behavioral Level in Verilog (Case)

There’s a 1:1 mapping between decimal digits, 8421 BCD, and 2421 BCD:

Digit    8 4 2 1    2 4 2 1
-----    -------    -------
  0      0 0 0 0    0 0 0 0
  1      0 0 0 1    0 0 0 1
  2      0 0 1 0    0 0 1 0
  3      0 0 1 1    0 0 1 1
  4      0 1 0 0    0 1 0 0
  5      0 1 0 1    1 0 1 1
  6      0 1 1 0    1 1 0 0
  7      0 1 1 1    1 1 0 1
  8      1 0 0 0    1 1 1 0
  9      1 0 0 1    1 1 1 1











/*
There’s a 1:1 mapping between decimal digits, 
8421 BCD, and 2421 BCD:

Digit    8 4 2 1    2 4 2 1
-----    -------    -------
  0      0 0 0 0    0 0 0 0
  1      0 0 0 1    0 0 0 1
  2      0 0 1 0    0 0 1 0
  3      0 0 1 1    0 0 1 1
  4      0 1 0 0    0 1 0 0
  5      0 1 0 1    1 0 1 1
  6      0 1 1 0    1 1 0 0
  7      0 1 1 1    1 1 0 1
  8      1 0 0 0    1 1 1 0
  9      1 0 0 1    1 1 1 1

*/

module BCD_2421(B,Y);

input  [3:0]B;  // B  4位元輸入
output [3:0]Y;   // Y    4位元輸出
reg [3:0]Y;

always@(*)begin
 case (B)  
    4'b0000: Y=4'b0000;  
    4'd1: Y=4'b0001; 
    4'd2: Y=4'b0010;  
    4'd3: Y=4'b0011;  
    4'd4: Y=4'b0100; 
    4'd5: Y=4'b0101;   
    4'd6: Y=4'b1100; 
    4'd7: Y=4'b1101;  
    4'd8: Y=4'b1110; 
    4'd9: Y=4'b1111;
    default: Y=4'bZZZZ;      
 endcase 

end

endmodule





//==========================================




// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps 
module TB;
/*
module BCD_2421(B,Y);
input  [3:0]B;  // B  4位元輸入
output [3:0]Y;   // Y    4位元輸出
*/
reg [3:0]B= 4'b0000;   //  暫存器資料初值為‘0’

wire [3:0]Y;

integer i;

BCD_2421 DUT(B,Y);

initial begin
    for (i=0; i<16; i=i+1) begin
         B = i;
         #20;
    end
    #20
     $stop;
end

endmodule