2-1 Multiplexer 多工器 (Gate Level)

2-1 Multiplexer 多工器 (Gate Level)

//------------------------------------
// 2-1 Multiplexer (Gate Level)
// Filename: mux_2to1.v
//------------------------------------
module  mux_2to1(a,b,s,y);

// Port Declarations
input a, b ,s ; // Data in : a, b;  Select: s
output y;  //output y


//Internal signal declarations
wire s0, sa, sb;

// Gate instantiations
not (s0, s);

// And gates are instantiated
and (sa, a, s0);
and (sb, b, s);
or (y, sa, sb);

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps

module TB;

/*
module  mux_2to1(a,b,s,y);
input a, b ,s ; // Data in : a, b;  Select: s
output y;  //output y
*/

//inputs
reg a=1'b0;
reg b=1'b0;
reg s=1'b0;

//outputs
wire y;

integer i=0;
//instantiate the design module and connect to the testbench variables
 mux_2to1 UUT (a,b,s,y);

initial
begin
for (i=0;i<=10;i=i+1)
begin
#50
{a,b,s}=i;
end
#50
$stop;

end
endmodule