2020年4月18日星期六

First project for QuartUS ii 9.1 sp2

First project for QuartUS ii 9.1

源自於 https://verilogguide.readthedocs.io/en/latest/verilog/firstproject.html

1.1. Introduction

In this tutorial, full adder is designed with the help of half adders. Here we will learn following methods to create/implement the digital designs using Altera-Quartus software,

Digital design using ‘block schematics’,
Digital design using ‘Verilog codes’,
Manual pin assignment for implementation,
Pin assignments using ‘.csv’ file,
Loading the design on FPGA.
Converting the ‘Verilog design’ to ‘Symbols’
Converting the ‘Block schematic’ to ‘Verilog code’ and ‘Symbols’.

If you do not have the FPGA-board, then skip the last part i.e. ‘loading the design on FPGA’. Simulation of the designs using ‘Modelsim’ is discussed in Chapter 2.

Quartus II 11.1sp2 Web Edition and ModelSim-Altera Starter software are used for this tutorial, which are freely available and can be downloaded from the Altera website. All the codes can be downloaded from the website. First line of each listing in the tutorial, is the name of the Verilog file in the downloaded zip-folder.

1.2. Creating the project

To create a new project, first open the Quartus and go to File–>New Project Wizard, as shown in Fig. 1.1.

Fig. 1.1 Create new project

‘Introduction’ window will appear after this, click ‘next’ and fill the project details as shown in Fig. 1.2.

Fig. 1.2 Name and location of project
After this, ‘Add files’ window will appear, click on ‘next’ here as we do not have any file to add to this project.
Next, ‘Family and Device settings’ page will appear, select the proper device setting based on your FPGA board and click ‘Finish’ as shown in Fig. 1.3. If you don’t have FPGA board, then simply click ‘Finish’.

Fig. 1.3 Devices settings

After clicking on finish, the project will be created as shown in Fig. 1.4. Note that, the tutorials are tested on DE2-115, DE2 (cyclone-II family) or DE0-Nano boards, therefore project settings may be different for different chapters. You need to select the correct device while running the code on your system. This can be done by double-clicking on the device name, as shown in Fig. 1.4.

Fig. 1.4 Update device settings (if required)

1.3. Digital design using ‘block schematics’

Digitals design can be create using two methods i.e. using ‘block-schematics’ and with ‘programming language e.g. VHDL or Verilog’ etc. Both have their own advantages in the design-process, as we will observe in the later chapters of the tutorial.

In this section, we will create a half_adder using block-schematics method, as shown below,

For this, click on File–>New–>Block diagram/Schematics files, as shown in Fig. 1.5; and a blank file will be created.

Fig. 1.5 Create new block schematics

Double click (anywhere) in the blank file, and a window will pop-up; select the ‘and’ gate from this window as shown in Fig. 1.6. Similarly, select the ‘xor’ gate.

Fig. 1.6 Select ‘and’ gate

Next, right click on the ‘xor’ gate and then click on ‘Generate Pins for Symbol Ports’, as shown in Fig. 1.7.

Fig. 1.7 Add ports

Now, connect the input ports of ‘xor’ gate with ‘and’ gate (using mouse); then Next, right click on the ‘and’ gate and then click on ‘Generate Pins for Symbol Ports’. Finally rename the input and output ports (i.e. x, y, sum and carry) as shown in Fig. 1.8.

Fig. 1.8 Make connections

Finally, save the design with name ‘half_adder_sch.bdf’. It’s better to save the design in the separate folder, so that we can distinguish the user-defined and system-generated files, as shown in Fig. 1.9 where Verilog codes are saved inside the ‘VerilogCodes’ folders, which is inside the main project directory.

Fig. 1.9 Save project in separate directory i.e. VerilogCodes here

Since the project name is ‘full_adder’, whereas the half adder’s design name is ‘half_adder_sch.bdf’ (i.e. not same as the project name), therefore we need to set this design as top level entity for compiling the project. For this, go to project navigator and right click on the ‘half_adder_sch.bdf’ and set it as top level entity, as shown in Fig. 1.10.

Fig. 1.10 Select top level entity for the project

Now, we can analyze the file as shown in Fig. 1.11. If all the connections are correct that analysis option will not show any error.

Note that, ‘start compilation’ option (above the Analyse option in the figure) is used when we want to generate the .sof/.pof file, to load the design on the FPGA, whereas analyze option is used to generate the RTL view only. We will use ‘compilation’ option in next section.

Fig. 1.11 Analyze the design

1.4. Manual pin assignment and compilation

Please enter correct pin location according to your FPGA board, as shown in this section. If you do not have the board, then skip this section and go to Section 1.6.

Once design is analyzed, then next step is to assign the correct pin location to input and output ports. This can be done manually or using .csv file. In this section, we will assign pin manually. Follow the below steps for pin assignments,

First open the ‘Pin-planner’ by clicking Assignments–>Pin Planner as shown in Fig. 1.12.

Fig. 1.12 Pin planner

Next, type the names of the input and output ports along with the pin-locations on the board, as shown in Fig. 1.13. Details of the Pin-locations are provided with the manual of the FPGA-boards e.g. in DE2-115 board, pin ‘PIN_AB28’ is connected with switch SW0. By assign this pin to ‘x’, we are connecting the port ‘x’ with switch SW0.

Fig. 1.13 Pin assignment

After assigning the pin, analyze the design again (see Fig. 1.11). After this, we can see the pin numbers in the ‘.bdf’ file, as shown in Fig. 1.14.

Fig. 1.14 Assigned pins to ports

Finally, compile the design using ‘ctrl+L’ button (or by clicking processing–>Start compilation, as shown in Fig. 1.15).

Fig. 1.15 Start compilation

After successful compilation, if we see the pin-assignment again, then we will find that direction of the pin are assigned now, as shown in Fig. 1.16 (which were set to ‘unknown’ during analysis as in Fig. 1.13)

Fig. 1.16 Direction of the ports

1.5. Load the design on FPGA

Follow the below, steps to load the design on FPGA,

Connect the FPGA to computer and turn it on.
Full compilation process generates the .sof/.pof files, which can be loaded on the FPGA board. To load the design on FPGA board, go to Tools–>Programmer. And a programmer window will pop up.
In the programmer window (see Fig. 1.17), look for two things i.e. position ‘1’ should display ‘USB-BLASTER’ and position ‘6’ should display the ‘.sof’ file. If any of this mission then follow below steps,
- If USB-BLASTER is missing, then click on ‘Hardware setup (location 2 in Fig. 1.17)’ and then double click on USB-BLASTER in the pop-up window (location 3). This will display the USB-BLASTER at location 4. Finally close the pop-up window.
- If ‘.sof’ file is not displayed at location 6, then click on ‘Add file…’ (location 7) and select the ‘.sof’ file from main project directory (or in output_files folder in main project directory).
Finally click on the ‘start’ button in Fig. 1.17 and check the operation of ‘half adder’ using switches SW0 and SW1; output will be displayed on green LEDs i.e. LEDG0 and LEDG1.

Fig. 1.17 Load the design on FPGA

1.6. Digital design using ‘Verilog codes’

In this section, half adder is implemented using Verilog codes. For this, click on File–>New–>Verilog files, as shown in Fig. 1.5; and a blank file will be created. Type the Listing Listing 1.1 in this file and save it as ‘half_adder_verilog.v’.

Now, set this design as ‘top level entity’ (Fig. 1.10). We can analyze the design now, but we will do it after assigning the pins using .csv file in next section.

Listing 1.1 Verilog code for half adder¶

// half_adder_verilog.v

module half_adder_verilog(
    input wire a, b,
    output wire sum, carry
);

assign sum = a ^ b;
assign carry = a & b;

endmodule

1.7. Pin assignments using ‘.csv’ file

In this section, we will learn to assign the pins using .csv files. Note that, we used input port as ‘a’ and ‘b’ in Verilog design (instead of ‘x’ and ‘y’ as in Fig. 1.8), so that we can observe the changes in the pin assignments.

To assign the pins using csv file, follow the below steps,

First type the content in Fig. 1.18 in a text-file and save it as ‘pin_assg_file.csv’.

Fig. 1.18 Content of pin_assg_file.csv

Next, click on the Assignments–>Import Assignments as shown in Fig. 1.19. And locate the file pin_assg_file.csv by clicking on the cdots button, in the popped-up window, as shown in Fig. 1.20.

Fig. 1.19 Import assignments

Fig. 1.20 Locate the csv file

Now, analyze the design (Fig. 1.11) and then open the pin planner (Fig. 1.12). We can see the new pin assignments as shown in Fig. 1.21 (If proper assignments do not happen, then check whether the Verilog design is set as top level or not and import assignments again and analyze the design).

Fig. 1.21 Pin assignments from csv file

Finally, compile and load and check the design as discussed in Section 1.5.

1.8. Converting the Verilog design to symbol

Verilog code can be converted into block schematic format, which is quite useful for connecting various modules together. In this section, half adder’s Verilog file is converted into schematic and then two half adder is connected to make a full adder. Note that, this connection can be made using Verilog code as well, which is discussed in Chapter 2.

Follow the below steps to create a full adder using this method,

Right click on the ‘half_adder_verilog.v’ and click on ‘Create symbol file for current file’ as shown in Fig. 1.22. It will create a symbol for half adder design.

Fig. 1.22 Convert Verilog code to symbol

Now, create a new ‘block schematic file’ (Fig. 1.5).
Next, double click on this file and add the half adder symbol as shown in Fig. 1.23.

Fig. 1.23 Add half adder symbol

Again add one more ‘half adder symbol’ along with ‘or’ gate and connect these components as shown in Fig. 1.24.

Fig. 1.24 Full adder using half adders

Since, one more port (i.e. c) is added to the design, therefore modify the ‘pin_assg_file.csv’ as shown in Fig. 1.25.

Fig. 1.25 Update pin assignments

Save the design as ‘full_adder_sch.bdf’.
Import the assignment again; and compile the design (see pin assignments as well for 5 ports i.e. a, b, c, sum and carry). Finally load the design on FGPA.

1.9. Convert Block schematic to ‘Verilog code’ and ‘Symbol’

We can convert the ‘.bdf’ file to Verilog code as well. In this section, full adder design is converted to Verilog code. For this open the file ‘full_adder_sch.bdf’. Then go to File–>Create/Update–>Create HDL Design File… as shown in Fig. 1.26 and select the file type as ‘Verilog’ and press OK; the file will be saved in the VerilogCodes folder (see Fig. 1.27). The content of the generated ‘Verilog’ file are shown in Listing 1.2.

Now, we can convert this Verilog code into symbol as shown in Section 1.8.

Note

Note that, if we want to convert the ‘.bdf’ file into symbol, then we need to convert it into Verilog code first, and then we can convert the Verilog code into symbol file.

Fig. 1.26 Convert schematic to Verilog

Fig. 1.27 Select Verilog

Listing 1.2 Verilog code for full adder¶

module full_adder_sch(
    a,
    b,
    c,
    sum,
    carry
);

input wire  a;
input wire  b;
input wire  c;
output wire sum;
output wire carry;

wire    SYNTHESIZED_WIRE_0;
wire    SYNTHESIZED_WIRE_1;
wire    SYNTHESIZED_WIRE_2;


half_adder_verilog  b2v_inst(
    .a(a),
    .b(b),
    .sum(SYNTHESIZED_WIRE_0),
    .carry(SYNTHESIZED_WIRE_1));


half_adder_verilog  b2v_inst2(
    .a(c),
    .b(SYNTHESIZED_WIRE_0),
    .sum(sum),
    .carry(SYNTHESIZED_WIRE_2));

assign  carry = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;


endmodule

1.10. Conclusion

In this chapter, we learn to implement the design using schematic and coding methods. Also, we did the pin assignments manually as well as using csv file. Finally, we learn to convert the Verilog code into symbol file; and schematic design into Verilog code.

Note

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2020年4月18日星期六