// divided by 8 with shif right operator ">>"
//filename : divid_8
module divide8(quot, div);
input [7:0] div; //dividend
output [7:0] quot; //quotient
parameter sh_bit = 3; //define the number of bits for shifting
assign quot = div >> sh_bit;
endmodule
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module TB;
/*
module divide8(quot, div);
input [7:0] div; //dividend
output [7:0] quot; //quotient
*/
reg [7:0] div;
wire[7:0] quot;
integer i;
divide8 UUT(quot, div);
initial begin
for ( i=150;i<=256;i=i+7)
begin
div = i;
#10;
end
end
endmodule
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