Four people voting （四人投票機）
•新增主席M
•
當平手時M才有列入計算
•
否則M不列入計算
四人投票機（查真值表）
新增一個主席M 當四人投票有結果反對或贊成時主席M不列入計算
當當四人投票結果為平手時主席M投票列入計算,使結果只能有反對或贊成
沒有平手
or not I0 and not I1 and not M
or not I0 and not I2 and not I3
or not I0 and not I2 and not M
or not I0 and not I3 and not M
or not I1 and not I2 and not I3
or not I1 and not I2 and not M
or not I1 and not I3 and not M
or not I2 and not I3 and not M;
O1 = I0 and I1 and I2
or I0 and I1 and I3
or I0 and I1 and M
or I0 and I2 and I3
or I0 and I2 and M
or I0 and I3 and M
or I1 and I2 and I3
or I1 and I2 and M
or I1 and I3 and M
or I2 and I3 and M;
//============================================
//Dataflow Level
/*
M I3 I2 I1 I0 O3
x 0 0 0 0 1 (0,16)
x 0 0 0 1 1 (1,17)
x 0 0 1 0 1 (2,18)
0 0 0 1 1 1 (3)
0 0 1 0 0 1 (4)
0 0 1 0 1 1 (5)
0 0 1 1 0 1 (6)
x 1 0 0 0 1 (8,24)
0 1 0 0 1 1 (9)
0 1 0 1 0 1 (10)
0 1 1 0 0 1; (12)
O3 = not I0 and not I1 and not I2
or not I0 and not I1 and not M
or not I0 and not I2 and not I3
or not I0 and not I2 and not M
or not I0 and not I3 and not M
or not I1 and not I2 and not I3
or not I1 and not I2 and not M
or not I1 and not I3 and not M
or not I2 and not I3 and not M;
*/
/*
' design comments
M I3 I2 I1 I0 O1
1 0 0 1 1 1 (19)
1 0 1 0 1 1 (21)
1 0 1 1 0 1 (22)
x 0 1 1 1 1 (7,23)
1 1 0 0 1 1 (25)
1 1 0 1 0 1 (26)
x 1 0 1 1 1 (11,27)
1 1 1 0 0 1 (28)
x 1 1 0 1 1 (13,29)
x 1 1 1 0 1 (14,30)
x 1 1 1 1 1; (15,31)
O1 = I0 and I1 and I2
or I0 and I1 and I3
or I0 and I1 and M
or I0 and I2 and I3
or I0 and I2 and M
or I0 and I3 and M
or I1 and I2 and I3
or I1 and I2 and M
or I1 and I3 and M
or I2 and I3 and M;
*/
module Voter(M,I,O3,O1);
input M;
input [3:0]I;
output O3,O1;
assign O1= (I[0]&I[1]&I[2]) |
(I[0]&I[1]&I[3]) |
(I[0]&I[1]&M) |
(I[0]&I[2]&I[3]) |
(I[0]&I[2]&M) |
(I[0]&I[3]&M) |
(I[1]&I[2]&I[3]) |
(I[1]&I[2]&M) |
(I[1]&I[3]&M) |
(I[2]&I[3]&M) ;
/*
O3 = not I0 and not I1 and not I2
or not I0 and not I1 and not M
or not I0 and not I2 and not I3
or not I0 and not I2 and not M
or not I0 and not I3 and not M
or not I1 and not I2 and not I3
or not I1 and not I2 and not M
or not I1 and not I3 and not M
or not I2 and not I3 and not M;
*/
assign O3= (~I[0] & ~I[1]& ~I[2]) |
(~I[0] & ~I[1]& ~M) |
(~I[0] & ~I[2]& ~I[3]) |
(~I[0] & ~I[2]& ~M) |
(~I[0] & ~I[3]& ~M) |
(~I[1] & ~I[2]& ~I[3]) |
(~I[1] & ~I[2]& ~M) |
(~I[1] & ~I[3]& ~M) |
(~I[2] & ~I[3]& ~M) ;
endmodule
//===============================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module T;
/*
module Voter(M,I,O3,O1);
input M;
input [3:0]I;
output O3,O1;
*/
// Inputs
reg [3:0]I=4'b0000;
reg M=1'b0;
// Outputs
wire O3,O1;
integer i;
// Instantiate the Unit Under Test (UUT)
Voter UUT(M,I,O3,O1);
initial begin
$monitor (M,I,O3,O1);
for(i=1; i<=35; i=i+1)
begin
#20 {M,I}=i;
end
end
endmodule
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