8-bit Arithmetic and Logic Unit

8-bit Arithmetic and Logic Unit (ALU)  in Verilog

源自於 https://esrd2014.blogspot.com/p/8-bit-arithmetic-and-logic-unit.html



`timescale 1ns / 1ps
module ALU_8bit( Opcode,Operand1,Operand2,Result,flagC,flagZ); 
input [2:0]  Opcode;
input [7:0]  Operand1,Operand2;
output reg [15:0] Result = 16'b0;
output reg  flagC = 1'b0,
            flagZ = 1'b0; 

parameter  [2:0] ADD = 3'b000,
                 SUB = 3'b001,
                 MUL = 3'b010,
                 AND = 3'b011,
                 OR = 3'b100,
                 NAND = 3'b101,
                 NOR = 3'b110,
                 XOR = 3'b111;   
always @ (Opcode or Operand1 or Operand2)
begin
 case (Opcode)
ADD: begin
Result = Operand1 + Operand2;
flagC  = Result[8];
flagZ  = (Result == 16'b0);
end
SUB: begin
Result = Operand1 - Operand2;
flagC  = Result[8];
flagZ  = (Result == 16'b0);
end
MUL: begin
Result = Operand1 * Operand2;
flagZ  = (Result == 16'b0);
end
AND: begin
Result = Operand1 & Operand2;
flagZ  = (Result == 16'b0);
end
OR:  begin
Result = Operand1 | Operand2;
flagZ  = (Result == 16'b0);
end
NAND: begin
Result = ~(Operand1 & Operand2);
flagZ  = (Result == 16'b0);
end
NOR: begin
Result = ~(Operand1 | Operand2);
flagZ  = (Result == 16'b0);
end
XOR: begin
Result = Operand1 ^ Operand2;
flagZ  = (Result == 16'b0);
end
default: begin
Result = 16'b0;
flagC  = 1'b0;
flagZ  = 1'b0;
end

 endcase

end
endmodule

//===============================

`timescale 1ns / 1ps

module ALU8bit_TB;

 // Inputs

 reg [2:0] Opcode;

 reg [7:0] Operand1;

 reg [7:0] Operand2;

 // Outputs

 wire [15:0] Result;

 wire flagC;

 wire flagZ;

 //Temporary variable

 reg [2:0] count = 3'd0;

 // Instantiate the Unit Under Test (UUT)

 ALU_8bit DUT (

  .Opcode(Opcode), 

  .Operand1(Operand1), 

  .Operand2(Operand2), 

  .Result(Result), 

  .flagC(flagC), 

  .flagZ(flagZ)

  );

 initial begin

  // Initialize Inputs

  Opcode   = 3'b0;

  Operand1 = 8'd0;

  Operand2 = 8'd0;

  // Wait 100 ns for global reset to finish

  #100;    

  // Add stimulus here  

  Operand1 = 8'hAA;

  Operand2 = 8'h55;  

  for (count = 0; count < 8; count = count + 1'b1) 

  begin

   Opcode = count;

   #20;

  end

 end     

endmodule