1 to 4 Demultiplexer in Verilog

1 to 4 Demultiplexer  in Verilog

//---------------------------------------------------------
//1 to 4 Demultiplexer using nesting if...else..statement
//---------------------------------------------------------
module DeMux_1x4(I, S0, S1 ,y );

input I;
input S0, S1;     //Selection signals
output reg [3:0] y;

always @ (I or S0 or S1)
  begin
    if (S1==1'b0)
      begin
    if (S0==1'b0)
           y = {3'b000, I};    //marge 000 with I to y
        else
           y = {2'b00, I, 1'b0};
  end
    else
      begin 
    if (S0==1'b0)
           y = {1'b0, I, 2'b00};
        else
           y = {I, 3'b000};
  end
  end

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module DeMux_1x4(I, S0, S1 ,y );
input I;
input S0, S1;     //Selection signals
output reg [3:0] y;
*/

// Inputs
    reg I;
    reg S0;
    reg S1;

// Outputs
    wire [3:0] y;

// Instantiate the UUT
DeMux_1x4 UUT (
        .y(y), 
        .I(I), 
        .S0(S0), 
        .S1(S1));

initial $monitor($time, "y = %b,  I = %b,  S0 = %b,  S1 = %b", y, I, S0, S1);
// Initialize Inputs
integer i,j;

initial begin
for (i=0;i<=3;i=i+1) begin
{S1,S0}=i;

for (j=0;j<=1;j=j+1) begin
I=j;
#20;
end
end
#20 
$stop;
end  
endmodule