verilog 8x1 multiplexer

verilog 8x1 multiplexer 

//============================
module Mux_8x1(a,sel,out);
input [7:0] a;
input [2:0] sel;
output out;

wire mux[2:0];

mux4to1 m1 (a[7:4],sel[1:0],mux_1);
mux4to1 m2 (a[3:0],sel[1:0],mux_2);
mux2to1 m3 (mux_1,mux_2,sel[2],out);

endmodule


module mux4to1(a,sel,out);
input [3:0] a;
input [1:0] sel;
output out;

wire mux[2:0];

mux2to1 m1 (a[3],a[2],sel[0],mux_1);
mux2to1 m2 (a[1],a[0],sel[0],mux_2);
mux2to1 m3 (mux_1,mux_2,sel[1],out);

endmodule

module mux2to1(a,b,sel,out);
input a,b,sel;
output out;
tri out;
bufif1 (out,a,sel);
bufif0 (out,b,sel);
endmodule


//============================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module TB;
/*

module Mux_8x1(a,sel,out);
input [7:0] a;
input [2:0] sel;
output out;
*/

// Inputs
reg [2:0]sel=3'b000;
reg [7:0]a  =8'b1010_0101;

// Outputs
wire out;

integer i;

// Instantiate the Unit Under Test (UUT)

Mux_8x1 UUT (a,sel,out);

initial begin
  $monitor (a,sel,out);
  // Initialize Inputs
end

initial begin

 for(i =0; i<=10; i=i+1)
begin
#20
sel=i;
end
  $stop;
 end

endmodule

//============================