8-bit Adders in Verilog (8位元加法器)

8-bit Adders in Verilog (8位元加法器)

Unsigned 8-bit Adder

This subsection contains a VHDL and Verilog description of an unsigned 8-bit Adder

The following table shows pin descriptions for an unsigned 8-bit Adder.

IO pins	Description
A[7:0], B[7:0]	Add Operands
SUM[7:0]	Add Result

Verilog

Following is the Verilog code for an unsigned 8-bit Adder.

module adder(A, B, SUM);  
input  [7:0] A;  
input  [7:0] B;  
output [7:0] SUM; 
 
  assign SUM = A + B;  
endmodule 

Unsigned 8-bit Adder with Carry In

This section contains VHDL and Verilog descriptions of an unsigned 8-bit adder with Carry In.

The following table shows pin descriptions for an unsigned 8-bit adder with carry.


IO pins

Description


A[7:0], B[7:0]

Add Operands


CI

Carry In


SUM[7:0]

Add Result

Verilog

Following is the Verilog code for an unsigned 8-bit adder with carry in.
module adder(A, B, CI, SUM);  
input  [7:0] A;  
input  [7:0] B;  
input  CI;  
output [7:0] SUM; 
 
  assign SUM = A + B + CI;  
endmodule 

Unsigned 8-bit Adder with Carry Out

This section contains VHDL and Verilog descriptions of an unsigned 8-bit adder with Carry Out.

If you use VHDL, then before writing a "+" operation with Carry Out,

please examine the arithmetic package you are going to use. 

For example "std_logic_unsigned" does not allow you to write "+" in the following form to obtain Carry Out:
Res(9-bit) = A(8-bit) + B(8-bit) 



The reason is that the size of the result for "+" in this package is equal to the size of the longest argument, that is, 8 bit.

One solution, for the example, is to adjust the size of operands A and B to 9-bit using concatenation


Res <= ("0" & A) + ("0" & B);

In this case, XST recognizes that this 9-bit adder can be implemented as an 8-bit adder with Carry Out.

Another solution is to convert A and B to integers and then convert the result back to the std_logic vector, specifying the size of the vector equal to 9:


The following table shows pin descriptions for an unsigned 8-bit adder with carry


IO pins

Description


A[7:0], B[7:0]

Add Operands


SUM[7:0]

Add Result


CO

Carry Out

Verilog

Following is the Verilog code for an unsigned 8-bit adder with carry out.
module adder(A, B, SUM, CO);  
input  [7:0] A;  
input  [7:0] B;  
output [7:0] SUM;  
output CO;  
wire [8:0] tmp; 
 
  assign tmp = A + B;  
  assign SUM = tmp [7:0];  
  assign CO  = tmp [8];  
endmodule 

Unsigned 8-bit Adder with Carry In and Carry Out

This section contains VHDL and Verilog code for an unsigned 8-bit adder with Carry In and Carry Out.

The following table shows pin descriptions for an unsigned 8-bit adder with carry.


IO pins

Description


A[7:0], B[7:0]

Add Operands


CI

Carry In


SUM[7:0]

Add Result


CO

Carry Out

Verilog

Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out.
module adder(A, B, CI, SUM, CO);  
input  CI;  
input  [7:0] A;  
input  [7:0] B;  
output [7:0] SUM;  
output CO;  
wire [8:0] tmp;  
  assign tmp = A + B + CI;  
  assign SUM = tmp [7:0];  
  assign CO  = tmp [8];  
endmodule 

Unsigned 8-bit Subtractor

The following table shows pin descriptions for an unsigned 8-bit subtractor.

IO pins	Description
A[7:0], B[7:0]	Sub Operands
RES[7:0]	Sub Result

Verilog

Following is the Verilog code for an unsigned 8-bit subtractor.

module subtr(A, B, RES);  
input  [7:0] A;  
input  [7:0] B;  
output [7:0] RES; 
 
  assign RES = A - B;  
endmodule 

Unsigned 8-bit Adder/Subtractor

The following table shows pin descriptions for an unsigned 8-bit adder/subtractor.

IO pins	Description
A[7:0], B[7:0]	Add/Sub Operands
OPER	Add/Sub Select
SUM[7:0]	Add/Sub Result

Verilog

Following is the Verilog code for an unsigned 8-bit adder/subtractor.

module addsub(A, B, OPER, RES);  
input  OPER;  
input  [7:0] A;  
input  [7:0] B;  
output [7:0] RES;  
reg    [7:0] RES; 
 
  always @(A or B or OPER)  
  begin  
    if (OPER==1'b0) RES = A + B;  
    else            RES = A - B;  
  end  
endmodule