(Generator 與 Checker 不同)
//============================================
//check even parity and zeros checker
//filename : even_parity.v
//============================================
module even_parity( din ,ev_parity, all_zeros);
input [7:0] din;
output ev_parity, all_zeros;
assign ev_parity = ~^ din;
assign all_zeros = ~| din;
endmodule
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module TB;
/*
module even_parity( din ,ev_parity, all_zeros);
input [7:0] din;
output ev_parity, all_zeros;
*/
reg [7:0] din;
wire ev_parity, all_zeros;
integer i;
even_parity UUT( din ,ev_parity, all_zeros);
initial begin
for ( i=0;i<=256;i=i+1)
begin
{din} = i;
#10;
end
end
endmodule
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