3-to-8 Decoder 解碼器 gate level in Verilog

3-to-8 Decoder 解碼器 gate level in Verilog

module Decoder(in,out);

input [2:0] in;
output [7:0] out;

wire in0_0,in0_1,in0_2;

not u1(in0_0,in[0]);
not u2(in0_1,in[1]);
not u3(in0_2,in[2]);

and u4 (out[0],in0_0,in0_1,in0_2);
and u5 (out[1],in[0],in0_1,in0_2);
and u6 (out[2],in0_0,in[1],in0_2);
and u7 (out[3],in[0],in[1],in0_2);
and u8 (out[4],in0_0,in0_1,in[2]);
and u9 (out[5],in[0],in0_1,in[2]);
and u10(out[6],in0_0,in[1],in[2]);
and u11(out[7],in[0],in[1],in[2]);

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module Decoder(in,out);

input [2:0] in;

output [7:0] out;

*/

reg [2:0] in;

wire [7:0] out;

integer i;

 

Decoder UUT(in,out);

 

initial begin  

   for ( i=0;i<=9;i=i+1) 

        begin

           {in}  = i;

            #1;

        end

end

endmodule