用bufif1 與 bufif0 組成的 4x1 Mux 多工器 verilog 程式

用bufif1 與 bufif0 組成的 4x1 Mux 多工器 verilog 程式 

//============================
//------------------------------------
// 4-1 Multiplexer with bufif0 and bufif1(Gate Level)
// Filename: mux_4x1_buffer.v
//------------------------------------
module mux_4x1_buffer(y, s, i);

// Port Declarations
output y;  //output y
input [1:0] s; // Data in : a, b;  Select: s
input [3:0] i;

//Internal signal declarations
wire y0, y1;

// Instantiates buffers
bufif0 (y0, i[0], s[0]);
bufif1 (y0, i[1], s[0]);
bufif0 (y1, i[2], s[0]);
bufif1 (y1, i[3], s[0]);
bufif0 (y, y0, s[1]);
bufif1 (y, y1, s[1]);
endmodule

//============================

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module mux_4x1(y, s, i);

output y;  //output y

input [1:0] s; // Data in : a, b;  Select: s

input [3:0] i;

*/

//inputs

reg [3:0]i=4'b0000;

reg [1:0]s=2'b00;

//outputs

wire y;

integer k=0,j=0;

//instantiate the design module and connect to the testbench variables

mux_4x1_buffer UUT(y, s, i);

initial

begin

for (k=0;k<=3;k=k+1)

begin

for (j=0;j<=15;j=j+1)

begin

#50 

s=k;

i=j;

end

end

#50 

$stop;

end

endmodule