Half Adder Dataflow Model in Verilog

Half Adder Dataflow Model in Verilog  

源自於 https://electronicstopper.blogspot.com/2017/06/half-adder-dataflow-model-in-verilog.html

Code:

module half_adder (input a, b, output s, c);
assign s = a ^ b;
assign c = a & b;
endmodule 

Testbench Code:

module half_adder_verilog_tb();

reg a, b;
wire s, c;

half_adder dut (.a(a), .b(b), .s(s), .c(c));

initial
begin

a = 1'b0;
b = 1'b0;
#50;

a = 1'b0;
b = 1'b1;
#50;

a = 1'b1;
b = 1'b0;
#50;

a = 1'b1;
b = 1'b1;

end

endmodule

Output: