Non-blocking Procedural Assignment in Verilog

Non-blocking Procedural Assignment in Verilog

//--------------------------------------------------
//4-bit register for Non-blocking Procedural Assignment
//--------------------------------------------------
module Nonblocking( CLK, RESET, Din,Qout);
input CLK, RESET;
input Din;
output reg [3:0] Qout;

always @ (posedge CLK or posedge RESET)
//Positive edge CLK and asynchronous RESET
 if (RESET)
   Qout <= 4'b0000;
 else
  begin
   Qout[0] <= Din;
   Qout[1] <= Qout[0];
   Qout[2] <= Qout[1];
   Qout[3] <= Qout[2];
  end
endmodule

//======================================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Nonblocking( CLK, RESET, Din,Qout);

input CLK, RESET;

input Din;

output reg [3:0] Qout;

*/

// Inputs

    reg CLK;

    reg RESET;

    reg Din;

// Outputs

    wire [3:0] Qout;

// Instantiate the UUT

Nonblocking UUT (

        .Qout(Qout), 

        .CLK(CLK), 

        .RESET(RESET), 

        .Din(Din)

        );

initial

 $monitor ($time, "Data in=%b,  CLK=%b,  RESET=%b, Qout=%b", Din, CLK, RESET, Qout);

initial //Initialize input signals

 begin

    CLK = 0;

    RESET = 1;

    Din = 0;

 end

initial 

 begin

   #35  RESET=0;          //Disable RESET at 35 ns

   #50  Din = 1;             //Set Din at different times

   #100 Din = 0;

   #75  Din = 1;

 end

always #10 CLK=~CLK;     //Set clock with a period 20 ns

initial #300 $finish;        //Complete simulation after 400 ns

  

endmodule