4-bit 3 to 1 multiplexer with priority
//---------------------------------------
//4-bit 3 to 1 multiplexer with priority
//---------------------------------------
module MUX_3x1_Priority(y, sel, a, b, c);
input [2:0] sel;
input [3:0] a, b, c;
output reg [3:0] y;
always @ (sel or a or b or c)
begin
casez (sel)
3'bzz1 : y=a;
3'bz10 : y=b;
3'b100 : y=c;
default : y=4'bzzzz;
endcase
end
endmodule
// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps
module TB;
/*
module MUX_3x1_Priority(y, sel, a, b, c);
input [2:0] sel;
input [3:0] a, b, c;
output reg [3:0] y;
*/
// Inputs
reg [2:0] sel;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
// Outputs
wire [3:0] y;
// Instantiate the UUT
MUX_3x1_Priority UUT (.y(y), .sel(sel), .a(a), .b(b), .c(c));
// Montoring signals
initial $monitor($time, "y=%h, sel=%b, a=%h, b=%h, c=%h", y, sel, a, b, c);
// Initialize Inputs
initial begin
sel = 3'b000;
a = 4'b0000;
b = 4'b1010;
c = 4'b1111;
end
always
#10 sel = sel + 3'h1;
initial #80 $finish; //Complete simulation after 160 units
endmodule
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