//=====================================================
// 4bit comparator using = operator (Dataflow level)
//=====================================================
module comp_4bit(a,b,Result);
input [3:0] a,b;
output [2:0] Result;
reg [2:0]tmp;
always @(*) begin
if (a>b)
tmp<=3'b100; //a>b
else if (a==b)
tmp<=3'b010; //a=b
else
tmp<=3'b001; //a<b
end
assign Result=tmp;
endmodule
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module TB;
/*
module comp_4bit(a,b,Result);
input [3:0] a,b;
output [2:0] Result;
*/
reg [3:0] a,b;
wire [2:0] Result;
integer i;
comp_4bit UUT(a,b,Result);
initial begin
for ( i=0;i<=256;i=i+1)
begin
{a,b} = i;
#1;
end
end
endmodule
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