Mux 2x1 in verilog

Mux 2x1  in verilog 

//=============================
module mux_2x1(s,a,b,out);
input s;
input [1:0] a;
input [1:0] b;
output [1:0] out;

mux2to1 u1(.a(a[0]),.b(a[1]),.sel(s),.out(out[0]));
mux2to1 u2(.a(b[0]),.b(b[1]),.sel(s),.out(out[1]));

endmodule


module mux2to1(a,b,sel,out);
input a,b,sel;
output out;
tri out;
bufif0 (out,a,sel);
bufif1 (out,b,sel);
endmodule

//==============================

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module TB;
/*
module mux_2x1( s, a, b, out);
input s;
input [1:0] a;
input [1:0] b;
output [1:0] out;
*/

reg s=1'b0;
reg [1:0]a=2'b00;
reg [1:0]b=2'b00;

wire [1:0]out;

integer i=0;

mux_2x1 UUT (s,a,b,out);

initial
begin
for (i=0;i<=5;i=i+1)
begin
#50
a[1:0]=i;
b[1:0]=i;
end

s=1'b1;

for (i=0;i<=5;i=i+1)
begin
#50
a[1:0]=i;
b[1:0]=i;
end

#50
$stop;
end
endmodule

//=====================
module mux_2x1(a,b,sel,out);
input a,b,sel;
output out;
tri out;
bufif1 (out,b,sel);
bufif0 (out,a,sel);
endmodule

//=====================

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module mux_2x1(a,b,sel,out);

input a,b,sel;

output out;

*/

reg sel=1'b0;

reg a=1'b0;

reg b=1'b0;

wire out;

mux_2x1 UUT (a,b,sel,out);

initial 

begin

#50

a=1'b0; b=1'b1;

#50

a=1'b1; b=1'b0;

#50

a=1'b1; b=1'b1;

//===================

#50

sel=1'b1; a=1'b0;b=1'b0;

#50

a=1'b0; b=1'b1;

#50

a=1'b1; b=1'b0;

#50

a=1'b1; b=1'b1;

//===================

#50 

$stop;

end

endmodule

//=====================