4 bits Full Adder 加法器 using 1 bit Full Adder (Gate Level)

4 bits Full Adder using 1 bit Full Adder (Gate Level)

//-------------------------------------------------------------
// 4 bits Full Adder using 1 bit Full Adder (Gate Level)
// Filename: FA_4bit.v
//-------------------------------------------------------------

module FA_4bit(a,b,cin,sum,cout);
input [3:0]a,b;
input cin;
output [3:0] sum;
output cout;
wire c1,c2,c3;

//Full_Adder(a,b,cin,sum,cout);
Full_Adder U1(a[0],b[0],cin,sum[0],c1);
Full_Adder U2(a[1],b[1],c1,sum[1],c2);
Full_Adder U3(a[2],b[2],c2,sum[2],c3);
Full_Adder U4(a[3],b[3],c3,sum[3],cout);

endmodule

module Full_Adder(a,b,cin,sum,cout);
//宣告輸出入埠
input a,b,cin;

output sum,cout;

//宣告內部接線
wire net1,net2,net3;

xor u0(sum, a, b, cin);
and u1(net1, a, b);
and u2(net2, b, cin);
and u3(net3, cin, a);
or u4 (cout, net1, net2, net3);
endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module FA_4bit(a,b,cin,sum,cout);

input [3:0]a,b;

input cin;

output [3:0] sum;

output cout;

*/

reg [3:0] a,b;

reg cin;

wire cout;

wire [3:0] sum;

integer i;

 

FA_4bit  UUT(a,b,cin,sum,cout);

 

initial begin  

   for ( i=0;i<=15;i=i+1) 

        begin

           a  = i;

           b  = i;

           cin=1'b0;

           #1;

        end

   for ( i=0;i<=15;i=i+1) 

        begin

           a  = i;

           b  = i;

           cin=1'b1;

           #1;

        end

   #2

$sto;

        

end

endmodule