2014年6月1日 星期日

Verilog (http://www.see.ed.ac.uk/)

http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/index.html

Contents



  1. Introduction
    1. Verilog
    2. The Manual
    3. Gate Types
  2. Lexicography
    1. White Space and Comments
    2. Operators
    3. Numbers
    4. Strings
  3. DataTypes
    1. Nets
    2. Registers
    3. Vectors
    4. Numbers
    5. Arrays
    6. Tri-state
  4. Operators
    1. Arithmetic
    2. Logical
    3. Relational
    4. Equality
    5. Bitwise
    6. Reduction
    7. Shift
    8. Concatenation and Replication
  5. System Tasks
    1. Output
    2. Monitoring a Stimulation
    3. Stopping a Simulation
  6. Large Worked Example: Multiplexor
    1. Introduction and Logic diargram
    2. Breakdown of Gate Level Description
    3. Breakdown of Logic Level Description
    4. Breakdown of Case Description
    5. Conditional Operator Implementation
    6. Stimulus for Multiplexor
  7. Modules
    1. Modules
    2. Stimulus
  8. Ports
    1. Port Lists
    2. Port Connections
  9. Basic Blocks
    1. Introduction to Procedural Contructs
    2. The initial Block
    3. The always Block
  10. Large Worked Example : Binary Counter
    1. Introduction and Logical Diagram
    2. Gate Level Description
    3. Behavioral Description
    4. The John Cooley Challenge
  11. Timing Control
    1. Delay Based
    2. Event Based
    3. Sensitivity (Trigger) List
    4. Gates : Information Propagation Delays
  12. Branches
    1. If-else
    2. Case Statement
    3. The Conditional Operator
  13. Loops
    1. Introduction to Looping Constructs
    2. While Loop
    3. For Loop
    4. Repeat Loop
    5. Forever Loop
  14. Extras
    1. Opening Files
    2. Writing to a File
    3. Closing a File
    4. Manipulating Memories Files
  15. Appendices
    1. Operator Precedance
    2. Keywords
    3. System Tasks and Functions
    4. Nets Types
    5. Creating Input Vectors

沒有留言:

張貼留言