利用2-4解碼器擴充到4-16解碼器---適用於DE2-70

利用SW[17]==> 致能Enable
SW[3] SW[2] SW[1] SW[0] 當成輸入信號 
輸出信號送至 LEDR[15:0]   

A 2-by-4 decoder has two input lines and four output lines, only one of which is logical 1 at any time. Which line is 1 depends on the input bit pair which can be 00,01,10,11.

So take two such 2-by-4 decoders which give you four input lines. Let the output lines be a0,a1,a2,a3 for one decoder and b0,b1,b2,b3 for the other. Use the 16 AND gates to compute the 16 functions ai∧bj,0≤i≤3,0≤j≤3. We now have a 4-by-16 circuit with the property that only one output is a logical 1 at any time: which one depends on the values of $i$ and $j$ which in turn depend on the 4 input bits. In other words, we have a 4-by-16 decoder constructed from two 2-by-4 decoders and 16 AND gates.

//適用於DE2-70 的程式
module Decoder4x16(
 input [17:0]SW,
 input [3:0] KEY,
 input  CLOCK_50,

 output [17:0] LEDR,
 output [7:0] LEDG,
 output [6:0] HEX0,
 output [6:0] HEX1,
 output [6:0] HEX2,
 output [6:0] HEX3,
 output [6:0] HEX4,
 output [6:0] HEX5,
 output [6:0] HEX6,
 output [6:0] HEX7
 );

assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
// assign LEDR[17:0]=SW[17:0];  //SW status =>LEDR
wire [3:0]Y,Y0,Y1,Y2,Y3;

decoder2_4 u1({SW[3],SW[2]},SW[17],Y);

decoder2_4 u2({SW[1],SW[0]},Y[0],Y0);
decoder2_4 u3({SW[1],SW[0]},Y[1],Y1);
decoder2_4 u4({SW[1],SW[0]},Y[2],Y2);
decoder2_4 u5({SW[1],SW[0]},Y[3],Y3);

assign LEDR[3:0]=Y0;
assign LEDR[7:4]=Y1;
assign LEDR[11:8]=Y2;
assign LEDR[15:12]=Y3;


endmodule


// File : 2 to 4 decoder using case statement.v
module decoder2_4 ( din ,ena ,dout );
input ena;
wire ena;

input [1:0] din ;
wire [1:0] din ;

output [3:0] dout ;
reg [3:0] dout ;


always @ (din or ena) begin
if (!ena) 
  dout=0;
 else begin 
 case (din)
  0 : dout = 1;
  1 : dout = 2;
  2 : dout = 4;
  default : dout = 8;
 endcase
 end
end

endmodule