Pipeline adder

Pipeline adder
http://blog.csdn.net/chevroletss/article/details/6289054

module PipeLine_Adder_16_bits(A,B,Clock,Reset,Cin,Sum,Cout);

input [15:0] A,B;

input Clock, Cin,Reset;

output [15:0]Sum;

output Cout;

reg [32:0]InPutReg;

reg [28:0]PipeLineReg_0;

reg [24:0]PipeLineReg_1;

reg [20:0]PipeLineReg_2;

reg [16:0]OutPutReg;

wire [3:0] Sum_0, Sum_1, Sum_2, Sum_3;

wire Cout_0,Cout_1,Cout_2,Cout_3;

always @(posedge Clock or negedge Reset )

begin

     if(!Reset)

       InPutReg <= 'd0;

    else

       InPutReg <= {B[15:12],A[15:12],B[11:8],A[11:8],B[7:4],A[7:4],B[3:0],A[3:0],Cin};

end

Carry_Look_Ahead_Adder u0(InPutReg[8:5],InPutReg[4:1],InPutReg[0],Sum_0, Cout_0);

always @(posedge Clock or negedge Reset)

begin

   if(!Reset)

      PipeLineReg_0 <= 'd0;

else

     PipeLineReg_0 <= {InPutReg[32:9],Cout_0, Sum_0};

end

Carry_Look_Ahead_Adder u1(PipeLineReg_0[12:9],PipeLineReg_0[8:5],PipeLineReg_0[4],Sum_1, Cout_1);

always @(posedge Clock or negedge Reset )

begin

if(!Reset)

    PipeLineReg_1 <= 'd0;

else

    PipeLineReg_1 <= {PipeLineReg_0[28:13],Cout_1, Sum_1,PipeLineReg_0[3:0]};

end

Carry_Look_Ahead_Adder u2(PipeLineReg_1[16:13],PipeLineReg_1[12:9],PipeLineReg_1[8],Sum_2, Cout_2);

always @(posedge Clock or negedge Reset )

begin

   if(!Reset)

     PipeLineReg_2 <= 'd0;

else

    PipeLineReg_2 <= {PipeLineReg_1[24:17],Cout_2,Sum_2,PipeLineReg_1[7:4],PipeLineReg_1[3:0]};

end

Carry_Look_Ahead_Adder u3(PipeLineReg_2[20:17],PipeLineReg_2[16:13],PipeLineReg_2[12],Sum_3, Cout_3);

always @(posedge Clock or negedge Reset )

begin

if(!Reset)

    OutPutReg <= 'd0;

else

   OutPutReg <= {Cout_3,Sum_3,PipeLineReg_2[11:0]};

end

assign {Cout,Sum} = OutPutReg;

endmodule