8-bit Register with Synchronous Reset

//8-bit Register with Synchronous Reset
module reg8 (reset, CLK, D, Q);
input reset;
input CLK;
input [7:0] D;
output [7:0] Q;
reg [7:0] Q;
always @(posedge CLK)
if (reset)
Q = 0;
else
Q = D;
endmodule // reg8



//N-bit Register with Asynchronous Reset Shift Register Example

module regN (reset, CLK, D, Q);
input reset;
input CLK;
parameter N = 8; // Allow N to be changed
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;
always @(posedge CLK or posedge reset)
if (reset)
Q = 0;
else if (CLK == 1)
Q = D;
endmodule // regN


// 8-bit register can be cleared, loaded, shifted left
// Retains value if no control signal is asserted
module shiftReg (CLK, clr, shift, ld, Din, SI, Dout);
input CLK;
input clr; // clear register 
input shift; // shift
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
output [7:0] Dout;
reg [7:0] Dout;
always @(posedge CLK) begin
if (clr) Dout <= 0;
else if (ld) Dout <= Din;
else if (shift) Dout <= { Dout[6:0], SI };
end
endmodule // shiftReg