2014年6月3日 星期二

Identifiers and Keywords

Identifiers and Keywords

// and ends with a new-line. 
/* and ends with the two characters */
Identifiers
Identifiers are names that are given to elements such as modules, registers, ports, wires, instances, and procedural blocks.

Verilog is case sensitive, ie Upper and lower case letters are considered to be different.

Examples of escaped identifiers include:
 \flip-flop
 \a+b

Verilog Keywords
always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodule
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor

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