MCP3002 ADC Module (Interlaced) --Verilog

2.7V Dual Channel 10-Bit A/D Converter with SPI™ Serial Interface
Features
• 10-bit resolution
• ±1 LSB max DNL
• ±1 LSB max INL 
• Analog inputs programmable as single-ended or 
pseudo-differential pairs
• On-chip sample and hold
• SPI™ serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 200 ksps max sampling rate at VDD = 5V
• 75 ksps max sampling rate at VDD = 2.7V
• Low power CMOS technology:
- 5 nA typical standby current, 2 µA max
- 550 µA max. active current at 5V
• Industrial temp range: -40°C to +85°C 
• 8-pin MSOP, PDIP, SOIC and TSSOP packages
Applications
• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems

源自於
https://gist.github.com/jjcarrier/2590356

module adc(clk, cs, clk_1_20, dout, din);

input  clk;     //p181

output  cs;    //p22

output  clk_1_20;   //p24

input  dout;    //p26

output  din;    //p28



wire clk;

wire dout;



reg clk_1_20;

reg din;

reg cs;

//----------------------------------------------------



//First generate the 1.2MHz clock from the 24MHz clock

//To do this we must create a counter that counts to 20

reg [4:0] cnt20; //This will create 32 values but we only want 20

reg [4:0] cnt20_next;



//Lets create the top level state update to cnt20

always @(posedge clk) cnt20<=cnt20_next;

//Lets create a simple process to limit this range

always @(posedge clk) 

begin

 if (cnt20==20) 

 begin

  cnt20_next<=0; //Reset to zero

  clk_1_20<=~clk_1_20; //Flip the state of clk_1_20

 end

 else 

 begin

  cnt20_next<=cnt20_next+1; //Continue with increment

  clk_1_20<=clk_1_20; //Maintain the state of clk_1_20

 end

end



//----------------------------------------------------

//In this code we will be using both the positive and negative edge 

//of the clk_1_20 signal. The order that these processes execute are important

//because of this we need to ensure that the negative edge processes start 

//before the postive edge processes. To do this we must create a latch signal.

reg init_latch;

always @(posedge clk_1_20) init_latch<=1;







//----------------------------------------------------

//Now that we have the 1.2MHz clock, we can generate

//another counter that counts to 16 at 1.2MHz

reg [3:0] cnt16;

always @(posedge clk_1_20) if (init_latch==1) cnt16<=cnt16+1; 



//----------------------------------------------------

//Lets also create a channel selection bit

//This bit will flip after each sample has been acquired

reg channel;

always @(negedge clk_1_20) if (init_latch==1) if (cnt16==15) channel<=~channel; else channel<=channel;



//----------------------------------------------------

//With the newly created counter, cnt16, 

//we can now create the 16 step SPI

//The input signals to the SPI should operate on the negative edge

//This is because the SPI on the ADC samples on the positive edge

//We want to maximize the settling time of the signal as to avoid

//communication errors

always @(negedge clk_1_20)

begin

 if (init_latch==1)

 begin

  case (cnt16)

  0://Bring cs high to initialize

   begin 

    cs<=1;

    din<=0;

   end

  1://START BIT :: Bring cs low and din high to initiate communication

   begin 

    cs<=0;

    din<=1;

   end

  2://MODE BIT :: Bring din high to set the mode to single-ended

   begin 

    cs<=0;

    din<=1;

   end

  3://CHANNEL BIT :: Bring din low to select channel 0

   begin 

    cs<=0;

    din<=0; //channel;

   end

  4://MSBF BIT :: Bring din high to set the output in MSB First format

   begin 

    cs<=0;

    din<=1;

   end

  5://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  6://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  7://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end



  8://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  9://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  10://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  11://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  12://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  13://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  14://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  15://Maintain cs low for the remainder of the 16 clocks

   begin 

    cs<=0;

    din<=0;

   end

  endcase

 end

end



//----------------------------------------------------

//Now that the input into the ADC's SPI has been created

//we can now grab the output

//First create the sample signal which will act as a 10-bit FIFO

reg [9:0] sample;



//----------------------------------------------------

//Now with the sample signal created, start sampling dout

//The output is only valid on clock 6-15

//This data should be grabbed on the positive edge so that

//the ADC's output has time to settle

//

always @(posedge clk_1_20)

begin

 if (init_latch==1)

 begin

  if (cnt16>=6)

  begin

   sample[9:1]<=sample[8:0];

   sample[0]<=dout;

  end

  else sample<=sample;

 end

end

endmodule