2014年6月3日 星期二

Overview of Verilog HDL

Overview of Verilog HDL




/* A simple AND gate 
File: and.v              */

module andgate (a, b, y);
input a, b;
output y;
assign y = a & b;
endmodule



/* testbench for AND gate 
File: and_tb.v */

module andgate_tb;
wire t_y;
reg t_a, t_b;

andgate my_gate( .a(t_a), .b(t_b), .y(t_y) );

initial
begin
$monitor(t_a, t_b, t_y); t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5  t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1;
end endmodule
IntegerMeaningStored as
5'b001015 bit binary 0010100101
8'b08 bit binary 0000000000000000
8'b1018 bit binary 0000010100000101
8'd58 bit decimal 500000101
8'h9f8 bit hex 9f10011111
3'd13 bit decimal 1001
4'bz3 bit decimal zzzzz
4'bx1binaryxxx1
5'b11zbinary0011z
1532 bit decimal 150....01111(32 bits)
'o532 bit octal 50....00101(32 bits)
Rules:
  • 1: Active high bit
  • 0: Active low bit
  • z: high impedance
  • x: Uncertain/ Don't care
  • If not mentioned, length is 32 bit and data type is integer by default.
  • If value is larger than the length, left most bits will be truncated
  • If value is smaller,
    • 0's are filled to the left if left most bit is 0 or 1
    • 'z' are filled if left most bit is z
    • 'x' are filled if left most bit is x

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