Verilog Code for IC74LS164 8-Bit Parallel-Out Serial Shift Registers -適用於DE2-70

module SIPO_8bit_shiftReg (CLK, clr, DinA, DinB, Dout);
input CLK;
input clr; // clear register 
input DinA,DinB; // Data input for load
output reg [7:0] Dout;

wire Din ;
assign Din=DinA & DinB ;

always @(negedge CLK or negedge clr) 
begin
 if (!clr) Dout <= 8'b0;
 else  Dout <= { Dout[6:0], Din };
end
endmodule // shiftReg



使module SIPO_8bit_shiftReg porting 到DE2-70 


module SIPO_8bits(
  input CLOCK_50,     //    50 MHz clock
  input [3:0] KEY,      //    Pushbutton[3:0]
  input [17:0] SW,     //    Toggle Switch[17:0]
  output [6:0]    HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits
  output [8:0] LEDG,   //    LED Green
  output [17:0] LEDR,   //    LED Red
  inout [35:0] GPIO_0,GPIO_1,    //    GPIO Connections
//    LCD Module 16X2
  output LCD_ON,     // LCD Power ON/OFF
  output LCD_BLON,     // LCD Back Light ON/OFF
  output LCD_RW,     // LCD Read/Write Select, 0 = Write, 1 = Read
  output LCD_EN,     // LCD Enable
  output LCD_RS,     // LCD Command/Data Select, 0 = Command, 1 = Data
  inout [7:0] LCD_DATA, // LCD Data bus 8 bits
  input  UART_RXD, //RS232 RXD
  output UART_TXD //RS232 TXD
);

//    All inout port turn to tri-state
assign    GPIO_0        =    36'hzzzzzzzzz;
assign    GPIO_1        =    36'hzzzzzzzzz;

assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;

//SIPO_8bit_shiftReg (CLK, clr, DinA,DinB,Dout);

SIPO_8bit_shiftReg (KEY[1],KEY[0],SW[1],SW[0],LEDR[7:0]);

endmodule



module SIPO_8bit_shiftReg (CLK, clr, DinA, DinB, Dout);
input CLK;
input clr; // clear register
input DinA,DinB; // Data input for load
output reg [7:0] Dout;

wire Din ;
assign Din=DinA & DinB ;

always @(negedge CLK or negedge clr)
begin
 if (!clr) Dout <= 8'b0;
 else  Dout <= { Dout[6:0], Din };
end
endmodule // shiftReg